diff --git a/artiq/examples/phaser/repository/test_ad9154_stpl.py b/artiq/examples/phaser/repository/test_ad9154_stpl.py
new file mode 100644
index 000000000..bc5cc40c4
--- /dev/null
+++ b/artiq/examples/phaser/repository/test_ad9154_stpl.py
@@ -0,0 +1,45 @@
+import time
+
+from artiq.coredevice.ad9154_reg import *
+from artiq.experiment import *
+
+
+class Test(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("ad9154")
+
+    def run(self):
+        self.stpl()
+
+    def stpl(self):
+        # short transport layer test
+        for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]):
+            # select dac
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+                AD9154_SHORT_TPL_TEST_EN_SET(0) |
+                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+                AD9154_SHORT_TPL_SP_SEL_SET(0))
+            # set expected value
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
+            # enable stpl
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+                AD9154_SHORT_TPL_TEST_EN_SET(1) |
+                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+                AD9154_SHORT_TPL_SP_SEL_SET(0))
+            # reset stpl
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+                AD9154_SHORT_TPL_TEST_EN_SET(1) |
+                AD9154_SHORT_TPL_TEST_RESET_SET(1) |
+                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+                AD9154_SHORT_TPL_SP_SEL_SET(0))
+            # release reset stpl
+            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+                AD9154_SHORT_TPL_TEST_EN_SET(1) |
+                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+                AD9154_SHORT_TPL_SP_SEL_SET(0))
+            print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)))
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 67bdc2ab8..56d9e97fe 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -543,6 +543,15 @@ class Phaser(_NIST_Ions):
                            "converter{}".format(i))
             # while at 5 GBps, take every second sample... FIXME
             self.comb += conv.eq(Cat(ch.o[::2]))
+
+        # short transport layer test pattern
+        self.comb += [
+            self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
+            self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
+            self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
+            self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
+        ]
+
         self.comb += jesd_sync.eq(self.ad9154.jesd_sync)