mirror of https://github.com/m-labs/artiq.git
sayma: remove SYSREF DDMTD core (#1420)
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@ -154,7 +154,7 @@ pub mod hmc7043 {
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(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
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(true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF
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(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(false, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(false, 0, 0x10, false), // 6: unused
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(true, SYSREF_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN
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@ -288,12 +288,6 @@ class Satellite(SatelliteBase):
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self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
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# DDMTD
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# https://github.com/sinara-hw/Sayma_RTM/issues/68
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sysref_pads = platform.request("amc_fpga_sysref", 1)
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
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self.csr_devices.append("sysref_ddmtd")
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class SimpleSatellite(SatelliteBase):
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def __init__(self, **kwargs):
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