mirror of https://github.com/m-labs/artiq.git
sayma_rtm: minor cleanup
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7f05e0c121
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29e5c95afa
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@ -102,6 +102,7 @@ class RTMScratch(Module, AutoCSR):
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read_data.status.eq(fifo.source.data)
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read_data.status.eq(fifo.source.data)
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]
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]
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CSR_RANGE_SIZE = 0x800
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CSR_RANGE_SIZE = 0x800
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@ -162,10 +163,7 @@ class SaymaRTM(Module):
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csr_devices.append("allaki_atts")
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csr_devices.append("allaki_atts")
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# HMC clock chip and DAC control
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# HMC clock chip and DAC control
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self.comb += [
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self.comb += platform.request("ad9154_rst_n").eq(1)
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platform.request("ad9154_rst_n").eq(1),
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]
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
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platform.request("hmc_spi"),
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platform.request("hmc_spi"),
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platform.request("ad9154_spi", 0),
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platform.request("ad9154_spi", 0),
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