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kc705: output divided-by-2 RTIO clock

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Sebastien Bourdeauducq 2015-07-27 20:46:44 +08:00
parent 256e99f0d7
commit 299bc1cb7e
1 changed files with 4 additions and 0 deletions
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4
soc/targets/artiq_kc705.py
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@ -60,6 +60,10 @@ class _RTIOCRG(Module, AutoCSR):
MultiReg(pll_locked, self._pll_locked.status) MultiReg(pll_locked, self._pll_locked.status)
] ]
# 62.5MHz when using internal RTIO clock
ext_clkout = platform.request("user_sma_gpio_p")
self.sync.rtio += ext_clkout.eq(~ext_clkout)
class _NIST_QCx(MiniSoC, AMPSoC): class _NIST_QCx(MiniSoC, AMPSoC):
csr_map = { csr_map = {