mirror of https://github.com/m-labs/artiq.git
pxi6733: minor mediator fixes
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63d4907c65
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2921bd6501
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@ -58,6 +58,9 @@ class _Segment:
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raise ArmError
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raise ArmError
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self.lines.append((duration, channel_data))
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self.lines.append((duration, channel_data))
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def get_sample_count(self):
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return sum(duration for duration, _ in self.lines)
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@kernel
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@kernel
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def advance(self):
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def advance(self):
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if self.frame.invalidated:
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if self.frame.invalidated:
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@ -107,13 +110,13 @@ class _Frame:
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self.invalidated = True
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self.invalidated = True
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def _get_samples(self):
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def _get_samples(self):
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program = [
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program = [[
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{
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{
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"dac_divider": 1,
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"dac_divider": 1,
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"duration": duration,
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"duration": duration,
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"channel_data": channel_data,
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"channel_data": channel_data,
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} for duration, channel_data in segment.lines
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} for segment in self.segments
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for segment in self.segments]
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for duration, channel_data in segment.lines]]
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synth = Synthesizer(self.daqmx.channel_count, program)
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synth = Synthesizer(self.daqmx.channel_count, program)
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synth.select(0)
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synth.select(0)
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# not setting any trigger flag in the program causes the whole
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# not setting any trigger flag in the program causes the whole
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@ -145,7 +148,7 @@ class CompoundDAQmx:
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self.daqmx = dmgr.get(daqmx_device)
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self.daqmx = dmgr.get(daqmx_device)
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self.clock = dmgr.get(clock_device)
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self.clock = dmgr.get(clock_device)
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self.channel_count = channel_count
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self.channel_count = channel_count
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if self.sample_rate_in_mu:
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if sample_rate_in_mu:
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self.sample_rate = sample_rate
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self.sample_rate = sample_rate
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else:
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else:
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self.sample_rate = self.clock.frequency_to_ftw(sample_rate)
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self.sample_rate = self.clock.frequency_to_ftw(sample_rate)
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