diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 80985c04a..8cd6b22ee 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -177,12 +177,31 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) + pmod = self.platform.request("pmod", 0) + + for i in range(4, 8): + phy = ttl_simple.Inout(pmod.d[i]) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128, + ofifo_depth=128)) + self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + spi_pins = Module() + spi_pins.cs_n = pmod.d[0] + spi_pins.mosi = pmod.d[1] + spi_pins.miso = pmod.d[2] + spi_pins.clk = pmod.d[3] + phy = spi.SPIMaster(spi_pins) + self.submodules += phy + self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.Channel.from_phy( + phy, ofifo_depth=128, ififo_depth=128)) + self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) self.config["DDS_CHANNEL_COUNT"] = 8 self.config["DDS_AD9858"] = True @@ -194,18 +213,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd ofifo_depth=512, ififo_depth=4)) - pmod = self.platform.request("pmod", 0) - spi_pins = Module() - spi_pins.clk = pmod.d[0] - spi_pins.mosi = pmod.d[1] - spi_pins.miso = pmod.d[2] - spi_pins.cs_n = pmod.d[3:] - phy = spi.SPIMaster(spi_pins) - self.submodules += phy - self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) - rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) - self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) diff --git a/artiq/gui/experiments.py b/artiq/gui/experiments.py index aeb4cfff4..0cb11bbe1 100644 --- a/artiq/gui/experiments.py +++ b/artiq/gui/experiments.py @@ -18,6 +18,15 @@ logger = logging.getLogger(__name__) # 2. file:@ +class _WheelFilter(QtCore.QObject): + def eventFilter(self, obj, event): + if (event.type() == QtCore.QEvent.Wheel and + event.modifiers() != QtCore.Qt.NoModifier): + event.ignore() + return True + return False + + class _ArgumentEditor(QtWidgets.QTreeWidget): def __init__(self, manager, dock, expurl): self.manager = manager @@ -38,6 +47,8 @@ class _ArgumentEditor(QtWidgets.QTreeWidget): self.setHorizontalScrollMode(QtWidgets.QAbstractItemView.ScrollPerPixel) self.setVerticalScrollMode(QtWidgets.QAbstractItemView.ScrollPerPixel) + self.viewport().installEventFilter(_WheelFilter(self.viewport())) + self._groups = dict() self._arg_to_entry_widgetitem = dict() diff --git a/artiq/gui/tools.py b/artiq/gui/tools.py index 97964bf4c..7782165d6 100644 --- a/artiq/gui/tools.py +++ b/artiq/gui/tools.py @@ -17,11 +17,11 @@ def log_level_to_name(level): class _WheelFilter(QtCore.QObject): def eventFilter(self, obj, event): - if event.type() == QtCore.QEvent.Wheel: + if (event.type() == QtCore.QEvent.Wheel and + event.modifiers() == QtCore.Qt.NoModifier): event.ignore() return True - else: - return False + return False def disable_scroll_wheel(widget): diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index c53ccbe23..8a947dab6 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -75,6 +75,20 @@ With the CLOCK hardware, the TTL lines are mapped as follows: | 21 | LA32_P | Clock | +--------------------+-----------------------+--------------+ +The board has RTIO SPI buses mapped as follows: + ++--------------+-------------+-------------+-----------+------------+ +| RTIO channel | CS_N | MOSI | MISO | CLK | ++==============+=============+=============+===========+============+ +| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK | ++--------------+-------------+-------------+-----------+------------+ +| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK | ++--------------+-------------+-------------+-----------+------------+ + NIST QC2 ++++++++ @@ -99,28 +113,45 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows: -+--------------+------------+------------+ -| RTIO channel | TTL line | Capability | -+==============+============+============+ -| 0 | PMT0 | Input | -+--------------+------------+------------+ -| 1 | PMT1 | Input | -+--------------+------------+------------+ -| 2-16 | TTL0-14 | Output | -+--------------+------------+------------+ -| 17 | EXT_LED | Output | -+--------------+------------+------------+ -| 18 | USER_LED_1 | Output | -+--------------+------------+------------+ -| 19 | USER_LED_2 | Output | -+--------------+------------+------------+ -| 20 | USER_LED_3 | Output | -+--------------+------------+------------+ -| 21 | USER_LED_4 | Output | -+--------------+------------+------------+ -| 22 | TTL15 | Clock | -+--------------+------------+------------+ ++--------------+------------+--------------+ +| RTIO channel | TTL line | Capability | ++==============+============+==============+ +| 0 | PMT0 | Input | ++--------------+------------+--------------+ +| 1 | PMT1 | Input | ++--------------+------------+--------------+ +| 2-16 | TTL0-14 | Output | ++--------------+------------+--------------+ +| 17 | EXT_LED | Output | ++--------------+------------+--------------+ +| 18 | USER_LED_1 | Output | ++--------------+------------+--------------+ +| 19 | USER_LED_2 | Output | ++--------------+------------+--------------+ +| 20 | USER_LED_3 | Output | ++--------------+------------+--------------+ +| 21 | USER_LED_4 | Output | ++--------------+------------+--------------+ +| 22 | PMOD_4 | Input+Output | ++--------------+------------+--------------+ +| 23 | PMOD_5 | Input+Output | ++--------------+------------+--------------+ +| 24 | PMOD_6 | Input+Output | ++--------------+------------+--------------+ +| 25 | PMOD_7 | Input+Output | ++--------------+------------+--------------+ +| 26 | TTL15 | Clock | ++--------------+------------+--------------+ The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention. The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2. + +The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD +Interface Type 2 (SPI) and 2A (expanded SPI): + ++--------------+--------+--------+--------+--------+ +| RTIO channel | CS_N | MOSI | MISO | CLK | ++==============+========+========+========+========+ +| 27 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | ++--------------+--------+--------+--------+--------+