From 27d94a22de9ba9d146ab897620858dd7618c07e0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 28 Apr 2015 01:38:11 +0800 Subject: [PATCH] rtio: expose full_ts_width instead of counter_width parameter --- artiq/gateware/rtio/core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 66abde0ee..96c382324 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -281,7 +281,7 @@ class _KernelCSRs(AutoCSR): class RTIO(Module): - def __init__(self, channels, clk_freq, counter_width=63, + def __init__(self, channels, clk_freq, full_ts_width=63, guard_io_cycles=20): data_width = max(rtlink.get_data_width(c.interface) for c in channels) @@ -293,7 +293,7 @@ class RTIO(Module): # CSRs self.kcsrs = _KernelCSRs(bits_for(len(channels)-1), data_width, address_width, - counter_width + fine_ts_width) + full_ts_width) # Clocking/Reset # Create rsys and rio domains based on sys and rio @@ -309,7 +309,7 @@ class RTIO(Module): self.kcsrs.reset.storage) # Managers - self.submodules.counter = _RTIOCounter(counter_width) + self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width) i_datas, i_timestamps = [], [] o_statuses, i_statuses = [], []