mirror of https://github.com/m-labs/artiq.git
transforms.iodelay_estimator: reject control flow in 'with parallel:' (fixes #195).
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@ -229,6 +229,23 @@ class IODelayEstimator(algorithm.Visitor):
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# inside a `with` statement after all.
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self.engine.process(error.cause)
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flow_stmt = None
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if self.current_goto is not None:
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flow_stmt = self.current_goto
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elif self.current_return is not None:
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flow_stmt = self.current_return
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if flow_stmt is not None:
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note = diagnostic.Diagnostic("note",
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"this '{kind}' statement transfers control out of "
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"the 'with parallel:' statement",
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{"kind": flow_stmt.keyword_loc.source()},
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flow_stmt.loc)
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diag = diagnostic.Diagnostic("error",
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"cannot interleave this 'with parallel:' statement", {},
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node.keyword_loc.join(node.colon_loc), notes=[note])
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self.engine.process(diag)
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elif len(node.items) == 1 and types.is_builtin(context_expr.type, "sequential"):
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self.visit(node.body)
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else:
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@ -0,0 +1,17 @@
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# RUN: %python -m artiq.compiler.testbench.signature +diag %s >%t
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# RUN: OutputCheck %s --file-to-check=%t
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def f():
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with parallel:' statement
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with parallel:
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# CHECK-L: ${LINE:+1}: note: this 'return' statement transfers control out of the 'with parallel:' statement
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return
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delay(1.0)
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def g():
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while True:
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# CHECK-L: ${LINE:+1}: error: cannot interleave this 'with parallel:' statement
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with parallel:
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# CHECK-L: ${LINE:+1}: note: this 'break' statement transfers control out of the 'with parallel:' statement
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break
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delay(1.0)
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