mirror of https://github.com/m-labs/artiq.git
phaser: make sysref input only for timing
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@ -22,7 +22,8 @@ from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.soc import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio, phaser
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from artiq.gateware import rtio
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from artiq.gateware.phaser import fmc_adapter_io
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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sawg)
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from artiq import __version__ as artiq_version
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@ -172,7 +173,7 @@ class Phaser(MiniSoC, AMPSoC):
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])
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platform = self.platform
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platform.add_extension(phaser.fmc_adapter_io)
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platform.add_extension(fmc_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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@ -201,7 +202,7 @@ class Phaser(MiniSoC, AMPSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sysref_pads = platform.request("ad9154_sysref")
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phy = ttl_serdes_7series.Inout_8X(sysref_pads.p, sysref_pads.n)
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phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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