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mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00

firmware: support DDRPHY without write leveling (fixes #886).

Currently, this is kasli.
This commit is contained in:
whitequark 2018-01-09 02:41:02 +00:00
parent 07ccb9eebd
commit 267c699835
4 changed files with 22 additions and 15 deletions

View File

@ -158,6 +158,7 @@ fn network_boot() {
println!("Using MAC address {} and IP address {}", eth_addr, ip_addr);
#[allow(unused_mut)]
let mut net_device = unsafe { ethmac::EthernetDevice::new() };
#[cfg(has_ethphy)]

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@ -8,13 +8,6 @@ mod ddr {
DFII_COMMAND_WRDATA, DFII_COMMAND_RDDATA};
use sdram_phy::{DFII_NPHASES, DFII_PIX_DATA_SIZE, DFII_PIX_WRDATA_ADDR, DFII_PIX_RDDATA_ADDR};
unsafe fn enable_write_leveling(enabled: bool) {
dfii::pi0_address_write(sdram_phy::DDR3_MR1 as u16 | ((enabled as u16) << 7));
dfii::pi0_baddress_write(1);
sdram_phy::command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
ddrphy::wlevel_en_write(enabled as u8);
}
#[cfg(kusddrphy)]
const DDRPHY_MAX_DELAY: u16 = 512;
#[cfg(not(kusddrphy))]
@ -30,6 +23,15 @@ mod ddr {
)
}
#[cfg(ddrphy_wlevel)]
unsafe fn enable_write_leveling(enabled: bool) {
dfii::pi0_address_write(sdram_phy::DDR3_MR1 as u16 | ((enabled as u16) << 7));
dfii::pi0_baddress_write(1);
sdram_phy::command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
ddrphy::wlevel_en_write(enabled as u8);
}
#[cfg(ddrphy_wlevel)]
unsafe fn write_level(logger: &mut Option<&mut fmt::Write>,
delay: &mut [u16; DQS_SIGNAL_COUNT],
high_skew: &mut [bool; DQS_SIGNAL_COUNT]) -> bool {
@ -102,6 +104,7 @@ mod ddr {
!failed
}
#[cfg(ddrphy_wlevel)]
unsafe fn read_bitslip(logger: &mut Option<&mut fmt::Write>,
delay: &[u16; DQS_SIGNAL_COUNT],
high_skew: &[bool; DQS_SIGNAL_COUNT]) {
@ -238,13 +241,16 @@ mod ddr {
}
pub unsafe fn level(logger: &mut Option<&mut fmt::Write>) -> bool {
let mut delay = [0; DQS_SIGNAL_COUNT];
let mut high_skew = [false; DQS_SIGNAL_COUNT];
if !write_level(logger, &mut delay, &mut high_skew) {
return false
#[cfg(ddrphy_wlevel)]
{
let mut delay = [0; DQS_SIGNAL_COUNT];
let mut high_skew = [false; DQS_SIGNAL_COUNT];
if !write_level(logger, &mut delay, &mut high_skew) {
return false
}
read_bitslip(logger, &delay, &high_skew);
}
read_bitslip(logger, &delay, &high_skew);
read_delays(logger);
true

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@ -148,7 +148,7 @@ fn startup_ethernet() {
}
}
let mut net_device = unsafe { ethmac::EthernetDevice::new() };
let net_device = unsafe { ethmac::EthernetDevice::new() };
// fn _net_trace_writer<U>(timestamp: u64, printer: smoltcp::wire::PrettyPrinter<U>)
// where U: smoltcp::wire::pretty_print::PrettyPrint {

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@ -15,7 +15,7 @@ requirements:
- python >=3.5.3,<3.6
- setuptools 33.1.1
- migen 0.6.dev py35_61+git31c446b
- misoc 0.8.dev py35_52+gitddbf9cbd
- misoc 0.8.dev py35_57+git3bfb128a
- jesd204b 0.4
- microscope
- binutils-or1k-linux >=2.27