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ad99xx unified type annotations for cfg_sw() methods and fixed test cases

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closes #1642

Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
This commit is contained in:
Leon Riesebos 2021-04-20 23:19:54 -04:00 committed by Sébastien Bourdeauducq
parent d745d50245
commit 2671c271d4
5 changed files with 10 additions and 10 deletions
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2
artiq/coredevice/ad9910.py
View File

@ -865,7 +865,7 @@ class AD9910:
return self.cpld.get_channel_att(self.chip_select - 4)
@kernel
def cfg_sw(self, state: TInt32):
def cfg_sw(self, state: TBool):
"""Set CPLD CFG RF switch state. The RF switch is controlled by the
logical or of the CPLD configuration shift register
RF switch bit and the SW TTL line (if used).

4
artiq/coredevice/ad9912.py
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@ -1,6 +1,6 @@
from numpy import int32, int64
from artiq.language.types import TInt32, TInt64, TFloat, TTuple
from artiq.language.types import TInt32, TInt64, TFloat, TTuple, TBool
from artiq.language.core import kernel, delay, portable
from artiq.language.units import ms, us, ns
from artiq.coredevice.ad9912_reg import *
@ -254,7 +254,7 @@ class AD9912:
return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_)
@kernel
def cfg_sw(self, state: TInt32):
def cfg_sw(self, state: TBool):
"""Set CPLD CFG RF switch state. The RF switch is controlled by the
logical or of the CPLD configuration shift register
RF switch bit and the SW TTL line (if used).

4
artiq/frontend/artiq_sinara_tester.py
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@ -225,13 +225,13 @@ class SinaraTester(EnvExperiment):
self.core.break_realtime()
channel.init()
channel.set(frequency*MHz)
channel.cfg_sw(1)
channel.cfg_sw(True)
channel.set_att(6.)
@kernel
def cfg_sw_off_urukul(self, channel):
self.core.break_realtime()
channel.cfg_sw(0)
channel.cfg_sw(False)
@kernel
def rf_switch_wave(self, channels):

2
artiq/test/coredevice/test_ad9910.py
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@ -182,7 +182,7 @@ class AD9910Exp(EnvExperiment):
self.core.break_realtime()
self.dev.cpld.init()
self.dev.init()
self.dev.cfg_sw(0)
self.dev.cfg_sw(False)
self.dev.sw.on()
sw_on = (self.dev.cpld.sta_read() >> (self.dev.chip_select - 4)) & 1
delay(10*us)

8
artiq/test/coredevice/test_urukul.py
View File

@ -39,9 +39,9 @@ class UrukulExp(EnvExperiment):
self.core.break_realtime()
self.dev.init()
self.dev.io_rst()
self.dev.cfg_sw(0, 0)
self.dev.cfg_sw(0, 1)
self.dev.cfg_sw(3, 1)
self.dev.cfg_sw(0, False)
self.dev.cfg_sw(0, True)
self.dev.cfg_sw(3, True)
self.dev.cfg_switches(0b1010)
@kernel
@ -51,7 +51,7 @@ class UrukulExp(EnvExperiment):
n = 10
t0 = self.core.get_rtio_counter_mu()
for i in range(n):
self.dev.cfg_sw(3, i & 1)
self.dev.cfg_sw(3, bool(i & 1))
self.set_dataset("dt", self.core.mu_to_seconds(
self.core.get_rtio_counter_mu() - t0) / n)