mirror of https://github.com/m-labs/artiq.git
runtime: fix Rust types in RTIO
Previous code assumed all RTIO registers were u32, but this was changed by misoc c5edcd08.
This commit is contained in:
parent
7fe5d737dd
commit
264d5fde83
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@ -4,12 +4,12 @@ use board::csr;
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use ::send;
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use ::send;
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use kernel_proto::*;
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use kernel_proto::*;
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pub const RTIO_O_STATUS_WAIT: u32 = 1;
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pub const RTIO_O_STATUS_WAIT: u8 = 1;
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pub const RTIO_O_STATUS_UNDERFLOW: u32 = 2;
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pub const RTIO_O_STATUS_UNDERFLOW: u8 = 2;
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pub const RTIO_O_STATUS_SEQUENCE_ERROR: u32 = 4;
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pub const RTIO_O_STATUS_SEQUENCE_ERROR: u8 = 4;
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pub const RTIO_I_STATUS_WAIT_EVENT: u32 = 1;
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pub const RTIO_I_STATUS_WAIT_EVENT: u8 = 1;
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pub const RTIO_I_STATUS_OVERFLOW: u32 = 2;
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pub const RTIO_I_STATUS_OVERFLOW: u8 = 2;
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pub const RTIO_I_STATUS_WAIT_STATUS: u32 = 4;
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pub const RTIO_I_STATUS_WAIT_STATUS: u8 = 4;
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pub extern fn init() {
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pub extern fn init() {
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send(&RtioInitRequest);
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send(&RtioInitRequest);
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@ -36,7 +36,7 @@ pub unsafe fn rtio_i_data_read(offset: usize) -> u32 {
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}
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}
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#[inline(never)]
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#[inline(never)]
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unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u32) {
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unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u8) {
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if status & RTIO_O_STATUS_WAIT != 0 {
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if status & RTIO_O_STATUS_WAIT != 0 {
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {}
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}
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}
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@ -54,11 +54,11 @@ unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u32)
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pub extern fn output(timestamp: i64, channel: i32, addr: i32, data: i32) {
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pub extern fn output(timestamp: i64, channel: i32, addr: i32, data: i32) {
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unsafe {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::chan_sel_write(channel as _);
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// writing timestamp clears o_data
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// writing timestamp clears o_data
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::o_address_write(addr as u32);
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csr::rtio::o_address_write(addr as _);
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rtio_o_data_write(0, data as u32);
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rtio_o_data_write(0, data as _);
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csr::rtio::o_we_write(1);
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csr::rtio::o_we_write(1);
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let status = csr::rtio::o_status_read();
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let status = csr::rtio::o_status_read();
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if status != 0 {
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if status != 0 {
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@ -69,12 +69,12 @@ pub extern fn output(timestamp: i64, channel: i32, addr: i32, data: i32) {
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pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice<i32>) {
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pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice<i32>) {
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unsafe {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::chan_sel_write(channel as _);
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// writing timestamp clears o_data
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// writing timestamp clears o_data
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::timestamp_write(timestamp as u64);
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csr::rtio::o_address_write(addr as u32);
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csr::rtio::o_address_write(addr as _);
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for i in 0..data.len() {
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for i in 0..data.len() {
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rtio_o_data_write(i, data[i] as u32)
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rtio_o_data_write(i, data[i] as _)
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}
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}
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csr::rtio::o_we_write(1);
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csr::rtio::o_we_write(1);
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let status = csr::rtio::o_status_read();
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let status = csr::rtio::o_status_read();
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@ -86,7 +86,7 @@ pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice<
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pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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unsafe {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::chan_sel_write(channel as _);
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csr::rtio::timestamp_write(timeout as u64);
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csr::rtio::timestamp_write(timeout as u64);
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csr::rtio::i_request_write(1);
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csr::rtio::i_request_write(1);
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@ -110,7 +110,7 @@ pub extern fn input_timestamp(timeout: i64, channel: i32) -> u64 {
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pub extern fn input_data(channel: i32) -> i32 {
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pub extern fn input_data(channel: i32) -> i32 {
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unsafe {
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unsafe {
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csr::rtio::chan_sel_write(channel as u32);
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csr::rtio::chan_sel_write(channel as _);
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csr::rtio::timestamp_write(0xffffffff_ffffffff);
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csr::rtio::timestamp_write(0xffffffff_ffffffff);
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csr::rtio::i_request_write(1);
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csr::rtio::i_request_write(1);
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