diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs
index f0330b4d9..a7259bc66 100644
--- a/artiq/firmware/runtime/rtio_clocking.rs
+++ b/artiq/firmware/runtime/rtio_clocking.rs
@@ -134,7 +134,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
             }
         },
         RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
-            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
+            info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
             si5324::FrequencySettings {
                 n1_hs  : 10,
                 nc1_ls : 4,
@@ -147,7 +147,7 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
             }
         },
         RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
-            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
+            info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
             si5324::FrequencySettings {
                 n1_hs  : 5,
                 nc1_ls : 8,