2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00

transforms.artiq_ir_generator: don't emit delay instruction for zero delay.

Call nodes with iodelay=Const(0) can be generated outside of
`with parallel:`, where Interleaver won't and LLVMIRGenerator can't
lower them.
This commit is contained in:
whitequark 2015-11-19 23:24:46 +08:00
parent 58db347e01
commit 2543daa5cf

View File

@ -8,7 +8,7 @@ semantics explicitly.
from collections import OrderedDict, defaultdict
from pythonparser import algorithm, diagnostic, ast
from .. import types, builtins, asttyped, ir
from .. import types, builtins, asttyped, ir, iodelay
def _readable_name(insn):
if isinstance(insn, ir.Constant):
@ -1619,7 +1619,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
attr_node = node.func
self.method_map[(attr_node.value.type, attr_node.attr)].append(insn)
if node.iodelay is not None:
if node.iodelay is not None and not iodelay.is_const(node.iodelay, 0):
after_delay = self.add_block()
self.append(ir.Delay(node.iodelay,
{var_name: self.current_args[var_name]