From 24b2bd7b6f325808d2a173e1cd95f2aca26cc954 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 11 Apr 2015 21:32:01 +0800 Subject: [PATCH] soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds --- soc/runtime/dds.h | 5 +++-- soc/targets/artiq_kc705.py | 29 +++++++++++++++++++---------- soc/targets/artiq_pipistrello.py | 28 +++++++++++++++++++--------- soc/targets/artiq_ppro.py | 13 ++++++++++--- 4 files changed, 51 insertions(+), 24 deletions(-) diff --git a/soc/runtime/dds.h b/soc/runtime/dds.h index 610499e02..fdbd8103f 100644 --- a/soc/runtime/dds.h +++ b/soc/runtime/dds.h @@ -2,12 +2,13 @@ #define __DDS_H #include +#include #define DDS_READ(addr) \ - MMPTR(0xb0000000 + (addr)*4) + MMPTR(DDS_BASE + (addr)*4) #define DDS_WRITE(addr, data) \ - MMPTR(0xb0000000 + (addr)*4) = data + MMPTR(DDS_BASE + (addr)*4) = data #define DDS_FTW0 0x0a #define DDS_FTW1 0x0b diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index c48bdb099..07187c381 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -34,6 +34,11 @@ class _Peripherals(MiniSoC): "rtiocrg": 13 } csr_map.update(MiniSoC.csr_map) + mem_map = { + "rtio": 0x20000000, # (shadow @0xa0000000) + "dds": 0x50000000, # (shadow @0xd0000000) + } + mem_map.update(MiniSoC.mem_map) def __init__(self, platform, cpu_type="or1k", **kwargs): MiniSoC.__init__(self, platform, @@ -74,17 +79,21 @@ class UP(_Peripherals): rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) - self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus) - self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) - - self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) + self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) + self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) + self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) + self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) class AMP(_Peripherals): csr_map = { "kernel_cpu": 14 } csr_map.update(_Peripherals.csr_map) + mem_map = { + "mailbox": 0x70000000 # (shadow @0xf0000000) + } + mem_map.update(_Peripherals.mem_map) def __init__(self, platform, *args, **kwargs): _Peripherals.__init__(self, platform, *args, **kwargs) @@ -92,15 +101,15 @@ class AMP(_Peripherals): self.submodules.kernel_cpu = amp.KernelCPU( platform, self.sdram.crossbar.get_master()) self.submodules.mailbox = amp.Mailbox() - self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1) - self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2) + self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) - self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus) - self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) - - self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) + self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) + self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) default_subtarget = AMP diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 02b889022..a6f70e431 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -51,6 +51,11 @@ class _Peripherals(BaseSoC): "rtiocrg": 13 } csr_map.update(BaseSoC.csr_map) + mem_map = { + "rtio": 0x20000000, # (shadow @0xa0000000) + "dds": 0x50000000, # (shadow @0xd0000000) + } + mem_map.update(MiniSoC.mem_map) def __init__(self, platform, cpu_type="or1k", **kwargs): BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs) @@ -93,17 +98,21 @@ class UP(_Peripherals): rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) - self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus) - self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) - - self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) + self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) + self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) + self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) + self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) class AMP(_Peripherals): csr_map = { "kernel_cpu": 14 } csr_map.update(_Peripherals.csr_map) + mem_map = { + "mailbox": 0x70000000 # (shadow @0xf0000000) + } + mem_map.update(_Peripherals.mem_map) def __init__(self, platform, *args, **kwargs): _Peripherals.__init__(self, platform, **kwargs) @@ -111,15 +120,16 @@ class AMP(_Peripherals): self.submodules.kernel_cpu = amp.KernelCPU( platform, self.sdram.crossbar.get_master()) self.submodules.mailbox = amp.Mailbox() - self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1) - self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2) + self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) - self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus) - self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) + self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) - self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) + self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) + self.kernel_cpu.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) default_subtarget = UP diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index f585c8815..b6168fc82 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -4,6 +4,7 @@ from migen.bank import wbgen from mibuild.generic_platform import * from misoclib.com import gpio +from misoclib.soc import mem_decoder from misoclib.mem.sdram.core.minicon import MiniconSettings from targets.ppro import BaseSoC @@ -59,6 +60,11 @@ class UP(BaseSoC): "rtiocrg": 13 } csr_map.update(BaseSoC.csr_map) + mem_map = { + "rtio": 0x20000000, # (shadow @0xa0000000) + "dds": 0x50000000, # (shadow @0xd0000000) + } + mem_map.update(MiniSoC.mem_map) def __init__(self, platform, cpu_type="or1k", with_test_gen=False, **kwargs): @@ -93,15 +99,16 @@ class UP(BaseSoC): rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wbgen.Bank(rtio_csrs) - self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) - self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs) + self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) + self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) if with_test_gen: self.submodules.test_gen = _TestGen(platform.request("ttl", 8)) dds_pads = platform.request("dds") self.submodules.dds = ad9858.AD9858(dds_pads) - self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus) + self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) + self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) self.comb += dds_pads.fud_n.eq(~fud)