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Commit missing parts of 948ed6fb.

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whitequark 2017-03-29 18:34:02 +00:00
parent 756e8a415e
commit 245e186347
1 changed files with 11 additions and 6 deletions
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17
artiq/test/coredevice/test_rtio.py
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@ -8,6 +8,7 @@ from math import sqrt
from artiq.experiment import * from artiq.experiment import *
from artiq.test.hardware_testbench import ExperimentCase from artiq.test.hardware_testbench import ExperimentCase
from artiq.coredevice import exceptions from artiq.coredevice import exceptions
from artiq.coredevice.comm_mgmt import CommMgmt
from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage, from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage,
decode_dump, get_analyzer_dump) decode_dump, get_analyzer_dump)
@ -387,18 +388,22 @@ class CoredeviceTest(ExperimentCase):
self.execute(SequenceError) self.execute(SequenceError)
def test_collision(self): def test_collision(self):
comm = self.device_mgr.get("core").comm core_addr = self.device_mgr.get_desc("comm")["arguments"]["host"]
comm.clear_log() mgmt = CommMgmt(self.device_mgr, core_addr)
mgmt.clear_log()
self.execute(Collision) self.execute(Collision)
log = comm.get_log() log = mgmt.get_log()
self.assertIn("RTIO collision", log) self.assertIn("RTIO collision", log)
mgmt.close()
def test_address_collision(self): def test_address_collision(self):
comm = self.device_mgr.get("core").comm core_addr = self.device_mgr.get_desc("comm")["arguments"]["host"]
comm.clear_log() mgmt = CommMgmt(self.device_mgr, core_addr)
mgmt.clear_log()
self.execute(AddressCollision) self.execute(AddressCollision)
log = comm.get_log() log = mgmt.get_log()
self.assertIn("RTIO collision", log) self.assertIn("RTIO collision", log)
mgmt.close()
def test_watchdog(self): def test_watchdog(self):
# watchdog only works on the device # watchdog only works on the device