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pdq: get new host driver, adapt
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artiq/devices/pdq/__init__.py
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1
artiq/devices/pdq/__init__.py
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@ -0,0 +1 @@
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from artiq.devices.pdq.mediator import *
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@ -1,4 +1,19 @@
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# Copyright (C) 2012-2015 Robert Jordens <jordens@gmail.com>
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# Copyright 2013-2017 Robert Jordens <jordens@gmail.com>
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#
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# This file is part of pdq.
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#
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# pdq is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# pdq is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with pdq. If not, see <http://www.gnu.org/licenses/>.
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from math import log, sqrt
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import logging
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@ -12,6 +27,65 @@ from artiq.wavesynth.coefficients import discrete_compensate
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logger = logging.getLogger(__name__)
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def discrete_compensate(c):
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"""Compensate spline coefficients for discrete accumulators.
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Given continuous-time b-spline coefficients, this function
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compensates for the effect of discrete time steps in the
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target devices.
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The compensation is performed in-place.
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"""
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l = len(c)
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if l > 2:
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c[1] += c[2]/2.
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if l > 3:
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c[1] += c[3]/6.
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c[2] += c[3]
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if l > 4:
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raise ValueError("Only splines up to cubic order are supported.")
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class CRC:
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"""Generic and simple table driven CRC calculator.
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This implementation is:
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* MSB first data
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* "un-reversed" full polynomial (i.e. starts with 0x1)
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* no initial complement
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* no final complement
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Handle any variation on those details outside this class.
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>>> r = CRC(0x1814141AB)(b"123456789") # crc-32q
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>>> assert r == 0x3010BF7F, hex(r)
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"""
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def __init__(self, poly, data_width=8):
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self.poly = poly
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self.crc_width = poly.bit_length() - 1
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self.data_width = data_width
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self._table = [self._one(i << self.crc_width - data_width)
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for i in range(1 << data_width)]
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def _one(self, i):
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for j in range(self.data_width):
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i <<= 1
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if i & 1 << self.crc_width:
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i ^= self.poly
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return i
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def __call__(self, msg, crc=0):
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for data in msg:
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p = data ^ crc >> self.crc_width - self.data_width
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q = crc << self.data_width & (1 << self.crc_width) - 1
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crc = self._table[p] ^ q
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return crc
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crc8 = CRC(0x107)
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class Segment:
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"""Serialize the lines for a single Segment.
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@ -49,6 +123,8 @@ class Segment:
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this line.
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silence (bool): Disable DAC clocks for the duration of this line.
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aux (bool): Assert the AUX (F5 TTL) output during this line.
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The corresponding global AUX routing setting determines which
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channels control AUX.
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shift (int): Duration and spline evolution exponent.
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jump (bool): Return to the frame address table after this line.
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clear (bool): Clear the DDS phase accumulator when starting to
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@ -134,17 +210,16 @@ class Segment:
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class Channel:
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"""PDQ2 Channel.
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"""PDQ Channel.
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Attributes:
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num_frames (int): Number of frames supported.
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max_data (int): Number of 16 bit data words per channel.
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segments (list[Segment]): Segments added to this channel.
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"""
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num_frames = 8
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max_data = 4*(1 << 10) # 8kx16 8kx16 4kx16
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def __init__(self):
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def __init__(self, max_data, num_frames):
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self.max_data = max_data
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self.num_frames = num_frames
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self.segments = []
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def clear(self):
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@ -220,38 +295,39 @@ class Channel:
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return self.table(entry) + data
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class Pdq2:
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class PdqBase:
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"""
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PDQ stack.
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Args:
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url (str): Pyserial device URL. Can be ``hwgrep://`` style
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(search for serial number, bus topology, USB VID:PID combination),
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``COM15`` for a Windows COM port number,
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``/dev/ttyUSB0`` for a Linux serial port.
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dev (file-like): File handle to use as device. If passed, ``url`` is
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ignored.
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num_boards (int): Number of boards in this stack.
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Attributes:
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num_dacs (int): Number of DAC outputs per board.
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checksum (int): Running checksum of data written.
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num_channels (int): Number of channels in this stack.
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num_boards (int): Number of boards in this stack.
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num_dacs (int): Number of DAC outputs per board.
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num_frames (int): Number of frames supported.
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channels (list[Channel]): List of :class:`Channel` in this stack.
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"""
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num_dacs = 3
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freq = 50e6
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_escape = b"\xa5"
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_commands = "RESET TRIGGER ARM DCM START".split()
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_mem_sizes = [None, (20,), (10, 10), (8, 6, 6)] # 10kx16 units
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def __init__(self, url=None, dev=None, num_boards=3):
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if dev is None:
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dev = serial.serial_for_url(url)
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self.dev = dev
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def __init__(self, num_boards=3, num_dacs=3, num_frames=32):
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"""Initialize PDQ stack.
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Args:
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num_boards (int): Number of boards in this stack.
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num_dacs (int): Number of DAC outputs per board.
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num_frames (int): Number of frames supported.
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"""
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self.checksum = 0
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self.num_boards = num_boards
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self.num_dacs = num_dacs
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self.num_frames = num_frames
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self.num_channels = self.num_dacs * self.num_boards
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self.channels = [Channel() for i in range(self.num_channels)]
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m = self._mem_sizes[num_dacs]
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self.channels = [Channel(m[j] << 11, num_frames)
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for i in range(num_boards)
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for j in range(num_dacs)]
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def get_num_boards(self):
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return self.num_boards
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@ -259,41 +335,71 @@ class Pdq2:
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def get_num_channels(self):
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return self.num_channels
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def get_num_frames(self):
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return self.num_frames
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def get_freq(self):
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return self.freq
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def set_freq(self, freq):
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self.freq = float(freq)
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def close(self):
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"""Close the USB device handle."""
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self.dev.close()
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del self.dev
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def _cmd(self, board, is_mem, adr, we):
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return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
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def write(self, data):
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"""Write data to the PDQ2 board.
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raise NotImplementedError
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def write_reg(self, board, adr, data):
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"""Write to a configuration register.
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Args:
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data (bytes): Data to write.
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board (int): Board to write to (0-0xe), 0xf for all boards.
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adr (int): Register address to write to (0-3).
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data (int): Data to write (1 byte)
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"""
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logger.debug("> %r", data)
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written = self.dev.write(data)
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if isinstance(written, int):
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assert written == len(data)
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self.write(struct.pack(
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"<BB", self._cmd(board, False, adr, True), data))
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def cmd(self, cmd, enable):
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"""Execute a command.
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def set_config(self, reset=False, clk2x=False, enable=True,
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trigger=False, aux_miso=False, aux_dac=0b111, board=0xf):
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"""Set the configuration register.
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Args:
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cmd (str): Command to execute. One of (``RESET``, ``TRIGGER``,
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``ARM``, ``DCM``, ``START``).
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enable (bool): Enable (``True``) or disable (``False``) the
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feature.
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reset (bool): Reset the board. Memory is not reset. Self-clearing.
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clk2x (bool): Enable the clock multiplier (100 MHz instead of 50
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MHz)
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enable (bool): Enable the channel data parsers and spline
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interpolators.
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trigger (bool): Soft trigger. Logical or with the hardware trigger.
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aux_miso (bool): Drive SPI MISO on the AUX/F5 ttl port of each
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board. If `False`, drive the masked logical or of the DAC
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channels' aux data.
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aux_dac (int): Mask for AUX/F5. Each bit represents one channel.
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AUX/F5 is: `aux_miso ? spi_miso :
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(aux_dac & Cat(_.aux for _ in channels) != 0)`
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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cmd = self._commands.index(cmd) << 1
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if not enable:
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cmd |= 1
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self.write(struct.pack("cb", self._escape, cmd))
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self.write_reg(board, 0, (reset << 0) | (clk2x << 1) | (enable << 2) |
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(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
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def set_checksum(self, crc=0, board=0xf):
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"""Set/reset the checksum register.
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Args:
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crc (int): Checksum value to write.
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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self.write_reg(board, 1, crc)
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def set_frame(self, frame, board=0xf):
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"""Set the current frame.
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Args:
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frame (int): Frame to select.
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board (int): Board to write to (0-0xe), 0xf for all boards.
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"""
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self.write_reg(board, 2, frame)
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def write_mem(self, channel, data, start_addr=0):
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"""Write to channel memory.
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@ -305,10 +411,8 @@ class Pdq2:
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start_addr (int): Start address to write data to.
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"""
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board, dac = divmod(channel, self.num_dacs)
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data = struct.pack("<HHH", (board << 4) | dac, start_addr,
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start_addr + len(data)//2 - 1) + data
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data = data.replace(self._escape, self._escape + self._escape)
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self.write(data)
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self.write(struct.pack("<BH", self._cmd(board, True, dac, True),
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start_addr) + data)
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def program_segments(self, segments, data):
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"""Append the wavesynth lines to the given segments.
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@ -372,18 +476,83 @@ class Pdq2:
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for channel, ch in zip(channels, chs):
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self.write_mem(channel, ch.serialize())
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def flush(self):
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self.dev.flush()
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def park(self):
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self.cmd("START", False)
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self.cmd("TRIGGER", True)
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def disable(self, **kwargs):
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"""Disable the device."""
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self.set_config(enable=False, **kwargs)
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self.flush()
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def unpark(self):
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self.cmd("TRIGGER", False)
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self.cmd("START", True)
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def enable(self, **kwargs):
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"""Enable the device."""
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self.set_config(enable=True, **kwargs)
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self.flush()
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def ping(self):
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"""Ping method returning True. Required for ARTIQ remote
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controller."""
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return True
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class Pdq(PdqBase):
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def __init__(self, url=None, dev=None, **kwargs):
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"""Initialize PDQ USB/Parallel device stack.
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Args:
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url (str): Pyserial device URL. Can be ``hwgrep://`` style
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(search for serial number, bus topology, USB VID:PID
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combination), ``COM15`` for a Windows COM port number,
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``/dev/ttyUSB0`` for a Linux serial port.
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dev (file-like): File handle to use as device. If passed, ``url``
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is ignored.
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**kwargs: See :class:`PdqBase` .
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"""
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if dev is None:
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dev = serial.serial_for_url(url)
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self.dev = dev
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PdqBase.__init__(self, **kwargs)
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def write(self, data):
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"""Write data to the PDQ board over USB/parallel.
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SOF/EOF control sequences are appended/prepended to
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the (escaped) data. The running checksum is updated.
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Args:
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data (bytes): Data to write.
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"""
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logger.debug("> %r", data)
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msg = b"\xa5\x02" + data.replace(b"\xa5", b"\xa5\xa5") + b"\xa5\x03"
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written = self.dev.write(msg)
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if isinstance(written, int):
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assert written == len(msg), (written, len(msg))
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self.checksum = crc8(data, self.checksum)
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def close(self):
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"""Close the USB device handle."""
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self.dev.close()
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del self.dev
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def flush(self):
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"""Flush pending data."""
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self.dev.flush()
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class PdqSPI(PdqBase):
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def __init__(self, dev=None, **kwargs):
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"""Initialize PDQ SPI device stack."""
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self.dev = dev
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PdqBase.__init__(self, **kwargs)
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def write(self, data):
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"""Write data to the PDQ board over USB/parallel.
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SOF/EOF control sequences are appended/prepended to
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the (escaped) data. The running checksum is updated.
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Args:
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data (bytes): Data to write.
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"""
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logger.debug("> %r", data)
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written = self.dev.write(data)
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if isinstance(written, int):
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assert written == len(data), (written, len(data))
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self.checksum = crc8(data, self.checksum)
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@ -154,10 +154,10 @@ class _Frame:
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self.pdq.next_segment = -1
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class CompoundPDQ2:
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def __init__(self, dmgr, pdq2_devices, trigger_device, frame_devices):
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class CompoundPDQ:
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def __init__(self, dmgr, pdq_devices, trigger_device, frame_devices):
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self.core = dmgr.get("core")
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self.pdq2s = [dmgr.get(d) for d in pdq2_devices]
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self.pdqs = [dmgr.get(d) for d in pdq_devices]
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self.trigger = dmgr.get(trigger_device)
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self.frame0 = dmgr.get(frame_devices[0])
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self.frame1 = dmgr.get(frame_devices[1])
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@ -172,7 +172,7 @@ class CompoundPDQ2:
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for frame in self.frames:
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frame._invalidate()
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self.frames.clear()
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for dev in self.pdq2s:
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for dev in self.pdqs:
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dev.park()
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self.armed = False
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@ -187,8 +187,8 @@ class CompoundPDQ2:
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full_program = self.get_program()
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n = 0
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for pdq2 in self.pdq2s:
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dn = pdq2.get_num_channels()
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for pdq in self.pdqs:
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dn = pdq.get_num_channels()
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program = []
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for full_frame_program in full_program:
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frame_program = []
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@ -201,10 +201,10 @@ class CompoundPDQ2:
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}
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frame_program.append(line)
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program.append(frame_program)
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pdq2.program(program)
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pdq.program(program)
|
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n += dn
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for pdq2 in self.pdq2s:
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pdq2.unpark()
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for pdq in self.pdqs:
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pdq.unpark()
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self.armed = True
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def create_frame(self):
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@ -1 +0,0 @@
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from artiq.devices.pdq2.mediator import *
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@ -172,30 +172,30 @@ device_db = {
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# that it always resolves to a network-visible IP address (see documentation).
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"host": "::1",
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"port": 4000,
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"command": "aqctl_pdq2 -p {port} --bind {bind} --simulation --dump qc_q1_0.bin"
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"command": "aqctl_pdq -p {port} --bind {bind} --simulation --dump qc_q1_0.bin"
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},
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"qc_q1_1": {
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"type": "controller",
|
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"host": "::1",
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"port": 4001,
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"command": "aqctl_pdq2 -p {port} --bind {bind} --simulation --dump qc_q1_1.bin"
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"command": "aqctl_pdq -p {port} --bind {bind} --simulation --dump qc_q1_1.bin"
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},
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"qc_q1_2": {
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"type": "controller",
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"host": "::1",
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"port": 4002,
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"command": "aqctl_pdq2 -p {port} --bind {bind} --simulation --dump qc_q1_2.bin"
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"command": "aqctl_pdq -p {port} --bind {bind} --simulation --dump qc_q1_2.bin"
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},
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"qc_q1_3": {
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"type": "controller",
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"host": "::1",
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"port": 4003,
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"command": "aqctl_pdq2 -p {port} --bind {bind} --simulation --dump qc_q1_3.bin"
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"command": "aqctl_pdq -p {port} --bind {bind} --simulation --dump qc_q1_3.bin"
|
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},
|
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"electrodes": {
|
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"type": "local",
|
||||
"module": "artiq.devices.pdq2",
|
||||
"class": "CompoundPDQ2",
|
||||
"module": "artiq.devices.pdq",
|
||||
"class": "CompoundPDQ",
|
||||
"arguments": {
|
||||
"pdq2_devices": ["qc_q1_0", "qc_q1_1", "qc_q1_2", "qc_q1_3"],
|
||||
"trigger_device": "ttl2",
|
||||
|
@ -4,18 +4,18 @@ import argparse
|
||||
import sys
|
||||
import time
|
||||
|
||||
from artiq.devices.pdq2.driver import Pdq2
|
||||
from artiq.devices.pdq.driver import Pdq
|
||||
from artiq.protocols.pc_rpc import simple_server_loop
|
||||
from artiq.tools import *
|
||||
|
||||
|
||||
def get_argparser():
|
||||
parser = argparse.ArgumentParser(description="PDQ2 controller")
|
||||
parser = argparse.ArgumentParser(description="PDQ controller")
|
||||
simple_network_args(parser, 3252)
|
||||
parser.add_argument("-d", "--device", default=None, help="serial port")
|
||||
parser.add_argument("--simulation", action="store_true",
|
||||
help="do not open any device but dump data")
|
||||
parser.add_argument("--dump", default="pdq2_dump.bin",
|
||||
parser.add_argument("--dump", default="pdq_dump.bin",
|
||||
help="file to dump simulation data into")
|
||||
parser.add_argument("-r", "--reset", default=False,
|
||||
action="store_true", help="reset device [%(default)s]")
|
||||
@ -37,16 +37,17 @@ def main():
|
||||
|
||||
if args.simulation:
|
||||
port = open(args.dump, "wb")
|
||||
dev = Pdq2(url=args.device, dev=port, num_boards=args.boards)
|
||||
dev = Pdq(url=args.device, dev=port, num_boards=args.boards)
|
||||
try:
|
||||
if args.reset:
|
||||
dev.write(b"\x00\x00") # flush any escape
|
||||
dev.cmd("RESET", True)
|
||||
dev.flush()
|
||||
dev.write(b"") # flush eop
|
||||
dev.set_config(reset=True)
|
||||
time.sleep(.1)
|
||||
dev.cmd("ARM", True)
|
||||
dev.park()
|
||||
simple_server_loop({"pdq2": dev}, bind_address_from_args(args),
|
||||
|
||||
dev.set_checksum(0)
|
||||
dev.checksum = 0
|
||||
|
||||
simple_server_loop({"pdq": dev}, bind_address_from_args(args),
|
||||
args.port, description="device=" + str(args.device))
|
||||
finally:
|
||||
dev.close()
|
||||
|
@ -4,34 +4,31 @@ import unittest
|
||||
import os
|
||||
import io
|
||||
|
||||
from artiq.devices.pdq2.driver import Pdq2
|
||||
from artiq.devices.pdq.driver import Pdq
|
||||
from artiq.wavesynth.compute_samples import Synthesizer
|
||||
|
||||
|
||||
pdq2_gateware = os.getenv("ARTIQ_PDQ2_GATEWARE")
|
||||
pdq_gateware = os.getenv("ARTIQ_PDQ_GATEWARE")
|
||||
|
||||
|
||||
class TestPdq2(unittest.TestCase):
|
||||
class TestPdq(unittest.TestCase):
|
||||
def setUp(self):
|
||||
self.dev = Pdq2(dev=io.BytesIO())
|
||||
self.dev = Pdq(dev=io.BytesIO())
|
||||
self.synth = Synthesizer(3, _test_program)
|
||||
|
||||
def test_reset(self):
|
||||
self.dev.cmd("RESET", True)
|
||||
self.dev.set_config(reset=True)
|
||||
buf = self.dev.dev.getvalue()
|
||||
self.assertEqual(buf, b"\xa5\x00")
|
||||
self.assertEqual(buf, b"\xa5\x02\xf8\xe5\xa5\x03")
|
||||
|
||||
def test_program(self):
|
||||
# about 0.14 ms
|
||||
self.dev.program(_test_program)
|
||||
|
||||
def test_cmd_program(self):
|
||||
self.dev.cmd("ARM", False)
|
||||
self.dev.cmd("START", False)
|
||||
self.dev.set_config(enable=False)
|
||||
self.dev.program(_test_program)
|
||||
self.dev.cmd("START", True)
|
||||
self.dev.cmd("ARM", True)
|
||||
# self.dev.cmd("TRIGGER", True)
|
||||
self.dev.set_config(enable=True, trigger=True)
|
||||
return self.dev.dev.getvalue()
|
||||
|
||||
def test_synth(self):
|
||||
@ -42,12 +39,12 @@ class TestPdq2(unittest.TestCase):
|
||||
|
||||
def run_gateware(self):
|
||||
import sys
|
||||
sys.path.append(pdq2_gateware)
|
||||
from gateware.pdq2 import Pdq2Sim
|
||||
from migen.sim.generic import run_simulation
|
||||
sys.path.append(pdq_gateware)
|
||||
from gateware.pdq import PdqSim
|
||||
from migen import run_simulation
|
||||
|
||||
buf = self.test_cmd_program()
|
||||
tb = Pdq2Sim(buf)
|
||||
tb = PdqSim()
|
||||
tb.ctrl_pads.trigger.reset = 1
|
||||
run_simulation(tb, ncycles=len(buf) + 250)
|
||||
delays = 7, 10, 30
|
||||
@ -57,7 +54,7 @@ class TestPdq2(unittest.TestCase):
|
||||
self.assertEqual(len(y[0]), 3)
|
||||
return y
|
||||
|
||||
@unittest.skipUnless(pdq2_gateware, "no pdq2 gateware")
|
||||
@unittest.skipUnless(pdq_gateware, "no PDQ gateware")
|
||||
def test_run_compare(self):
|
||||
y_ref = self.test_synth()
|
||||
y = self.run_gateware()
|
||||
@ -70,7 +67,7 @@ class TestPdq2(unittest.TestCase):
|
||||
self.assertAlmostEqual(yij, yij_ref, 2, "disagreement at "
|
||||
"t={}, c={}".format(i, j))
|
||||
|
||||
@unittest.skipUnless(pdq2_gateware, "no pdq2 gateware")
|
||||
@unittest.skipUnless(pdq_gateware, "no PDQ gateware")
|
||||
@unittest.skip("manual/visual test")
|
||||
def test_run_plot(self):
|
||||
from matplotlib import pyplot as plt
|
2
setup.py
2
setup.py
@ -39,7 +39,7 @@ console_scripts = [
|
||||
"aqctl_lda=artiq.frontend.aqctl_lda:main",
|
||||
"aqctl_novatech409b=artiq.frontend.aqctl_novatech409b:main",
|
||||
"aqctl_korad_ka3005p=artiq.frontend.aqctl_korad_ka3005p:main",
|
||||
"aqctl_pdq2=artiq.frontend.aqctl_pdq2:main",
|
||||
"aqctl_pdq=artiq.frontend.aqctl_pdq:main",
|
||||
"aqctl_thorlabs_tcube=artiq.frontend.aqctl_thorlabs_tcube:main",
|
||||
]
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user