mirror of https://github.com/m-labs/artiq.git
kc705: fix DRTIO targets
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5111132ef0
commit
242dfae38e
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@ -82,16 +82,75 @@ class _RTIOCRG(Module, AutoCSR):
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]
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# The default user SMA voltage on KC705 is 2.5V, and the Migen platform
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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# The default voltage for these signals on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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_sma33_io = [
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_reprogrammed3v3_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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("si5324_33", 0,
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Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS33")),
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Subsignal("int", Pins("AG24"), IOStandard("LVCMOS33"))
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),
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("sfp_tx_disable_n_33", 0, Pins("Y20"), IOStandard("LVCMOS33")),
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# HACK: this should be LVDS, but TMDS is the only supported differential
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# output standard at 3.3V. KC705 hardware design issue?
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("si5324_clkin_33", 0,
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Subsignal("p", Pins("W27"), IOStandard("TMDS_33")),
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Subsignal("n", Pins("W28"), IOStandard("TMDS_33"))
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),
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20"), Misc("PULLUP=TRUE")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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]
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_ams101_dac = [
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("ams101_dac", 0,
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Subsignal("ldac", Pins("XADC:GPIO0")),
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@ -102,17 +161,6 @@ _ams101_dac = [
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)
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]
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_sdcard_spi_33 = [
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20"), Misc("PULLUP=TRUE")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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]
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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@ -150,9 +198,8 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.platform.request("user_led", 1)))
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self.csr_devices.append("leds")
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_reprogrammed3v3_io)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_sdcard_spi_33)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -220,11 +267,10 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.platform.toolchain.bitgen_opt += " -g compress"
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platform = self.platform
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platform.add_extension(_sma33_io)
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platform.add_extension(_reprogrammed3v3_io)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_sdcard_spi_33)
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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@ -277,7 +323,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -307,6 +353,10 @@ class _MasterBase(MiniSoC, AMPSoC):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
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self.submodules.rtio_crg = _RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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@ -351,11 +401,10 @@ class _SatelliteBase(BaseSoC):
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self.platform.toolchain.bitgen_opt += " -g compress"
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platform = self.platform
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platform.add_extension(_sma33_io)
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platform.add_extension(_reprogrammed3v3_io)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_sdcard_spi_33)
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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@ -422,14 +471,14 @@ class _SatelliteBase(BaseSoC):
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self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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# Si5324 Phaser
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkin=platform.request("si5324_clkin_33"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -458,6 +507,10 @@ class _SatelliteBase(BaseSoC):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtx.rxoutclk)
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self.submodules.rtio_crg = _RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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