sayma: fix FTW for SyncDDS

2021-12-09 16:43:45 +08:00 · 2021-12-09 16:43:45 +08:00 · 23f5796d67
parent 34e89a3777
commit 23f5796d67
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@ -240,7 +240,7 @@ class JDCGSyncDDS(Module, AutoCSR):

        self.sawgs = []

-        ftw = round(2**len(self.coarse_ts)*9e6/600e6)
+        ftw = round(2**len(self.coarse_ts)*9e6/1000e6)
        parallelism = 8

        mul_1 = Signal.like(self.coarse_ts)