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sayma: fix FTW for SyncDDS

This commit is contained in:
Harry Ho 2021-12-09 16:43:45 +08:00
parent 34e89a3777
commit 23f5796d67
1 changed files with 1 additions and 1 deletions
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artiq/gateware/targets/sayma_amc.py
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@ -240,7 +240,7 @@ class JDCGSyncDDS(Module, AutoCSR):
self.sawgs = [] self.sawgs = []
ftw = round(2**len(self.coarse_ts)*9e6/600e6) ftw = round(2**len(self.coarse_ts)*9e6/1000e6)
parallelism = 8 parallelism = 8
mul_1 = Signal.like(self.coarse_ts) mul_1 = Signal.like(self.coarse_ts)