mirror of https://github.com/m-labs/artiq.git
dds: make init_sync accessible for AD9914 only
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@ -156,24 +156,6 @@ class _DDSGeneric:
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timing margin."""
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timing margin."""
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dds_init(now_mu(), self.bus_channel, self.channel)
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dds_init(now_mu(), self.bus_channel, self.channel)
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@kernel
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def init_sync(self, sync_delay=0):
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"""Resets and initializes the DDS channel as well as configures
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the AD9914 DDS for synchronisation. The synchronisation procedure
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follows the steps outlined in the AN-1254 application note.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 10ms provides a good
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timing margin.
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:param sync_delay: integer from 0 to 0x3f that sets value of
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SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits."""
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dds_init_sync(now_mu(), self.bus_channel, self.channel, sync_delay)
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@kernel
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@kernel
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def set_phase_mode(self, phase_mode):
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def set_phase_mode(self, phase_mode):
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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@ -236,3 +218,21 @@ class AD9914(_DDSGeneric):
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"""Driver for AD9914 DDS chips. See ``_DDSGeneric`` for a description
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"""Driver for AD9914 DDS chips. See ``_DDSGeneric`` for a description
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of the functionality."""
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of the functionality."""
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pow_width = 16
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pow_width = 16
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@kernel
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def init_sync(self, sync_delay=0):
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"""Resets and initializes the DDS channel as well as configures
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the AD9914 DDS for synchronisation. The synchronisation procedure
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follows the steps outlined in the AN-1254 application note.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 10ms provides a good
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timing margin.
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:param sync_delay: integer from 0 to 0x3f that sets value of
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SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits."""
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dds_init_sync(now_mu(), self.bus_channel, self.channel, sync_delay)
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