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gateware/targets/kasli: Set DRTIO_ROLE in {Master, Satellite}Base 

These were introduced in 82bd913f63, and for Kasli only set from
the JSON description in the *Generic subclasses. Not all firmware
is built through that API, however, e.g. the CI system at the
University of Oxford. The missing attribute breaks artiq.build_soc.
This commit is contained in:
David Nadlinger 2023-09-17 00:48:42 +01:00
parent fc74b78a45
commit 22ab62324c
1 changed files with 2 additions and 0 deletions
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artiq/gateware/targets/kasli.py
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@ -317,6 +317,7 @@ class MasterBase(MiniSoC, AMPSoC):
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.config["DRTIO_ROLE"] = "master"
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.gt_drtio.gtps[0]
@ -565,6 +566,7 @@ class SatelliteBase(BaseSoC, AMPSoC):
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.config["DRTIO_ROLE"] = "satellite"
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)