From 222968d68b0b63dc8b5cd209ed2743a55c759343 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 13 Nov 2021 12:42:13 +0800
Subject: [PATCH] coredevice: reinstate AugAssign methods

---
 artiq/coredevice/ad9912.py | 9 ++++-----
 artiq/coredevice/ttl.py    | 2 +-
 artiq/coredevice/urukul.py | 8 ++++----
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index f1c27077b..d8e35898f 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -89,8 +89,7 @@ class AD9912:
         self.bus.write(0)
         data = self.bus.read()
         if length < 4:
-            # NAC3TODO data &= (1 << (length * 8)) - 1
-            data = data & (1 << (length * 8)) - 1
+            data &= (1 << (length * 8)) - 1
         return data
 
     @kernel
@@ -120,7 +119,7 @@ class AD9912:
         self.cpld.io_update.pulse(2. * us)
         self.core.delay(1. * ms)
 
-    # NAC3TODO @kernel
+    @kernel
     def set_att_mu(self, att: int32):
         """Set digital step attenuator in machine units.
 
@@ -132,7 +131,7 @@ class AD9912:
         """
         self.cpld.set_att_mu(self.chip_select - 4, att)
 
-    # NAC3TODO @kernel
+    @kernel
     def set_att(self, att: float):
         """Set digital step attenuator in SI units.
 
@@ -262,7 +261,7 @@ class AD9912:
         # Convert and return
         return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_)
 
-    # NAC3TODO @kernel
+    @kernel
     def cfg_sw(self, state: bool):
         """Set CPLD CFG RF switch state. The RF switch is controlled by the
         logical or of the CPLD configuration shift register
diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
index 0aec996da..45c3d6fe9 100644
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@@ -307,7 +307,7 @@ class TTLInOut:
         self._set_sensitivity(0)
         return now_mu()
 
-    # NAC3TODO @kernel
+    @kernel
     def count(self, up_to_timestamp_mu: int64) -> int32:
         """Consume RTIO input events until the hardware timestamp counter has
         reached the specified timestamp and return the number of observed
diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py
index f329f0df7..21c3bbf34 100644
--- a/artiq/coredevice/urukul.py
+++ b/artiq/coredevice/urukul.py
@@ -265,7 +265,7 @@ class CPLD:
         self.cfg_write(self.cfg_reg | (1 << CFG_IO_RST))
         self.cfg_write(self.cfg_reg & ~(1 << CFG_IO_RST))
 
-    # NAC3TODO @kernel
+    @kernel
     def cfg_sw(self, channel: int32, on: bool):
         """Configure the RF switches through the configuration register.
 
@@ -311,7 +311,7 @@ class CPLD:
             pass
         return code
 
-    # NAC3TODO @kernel
+    @kernel
     def set_att_mu(self, channel: int32, att: int32):
         """Set digital step attenuator in machine units.
 
@@ -340,7 +340,7 @@ class CPLD:
         self.bus.write(att_reg)
         self.att_reg = att_reg
 
-    # NAC3TODO @kernel
+    @kernel
     def set_att(self, channel: int32, att: float):
         """Set digital step attenuator in SI units.
 
@@ -421,7 +421,7 @@ class CPLD:
         # NAC3TODO assert ftw * div == ftw_max
         self.sync.set_mu(ftw)
 
-    # NAC3TODO @kernel
+    @kernel
     def set_profile(self, profile: int32):
         """Set the PROFILE pins.