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sayma: use SFP0 for DRTIO master

This commit is contained in:
Sebastien Bourdeauducq 2019-10-16 17:53:40 +08:00
parent 6cf06fba7b
commit 21a1c6de3f
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/sayma_amc.py
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@ -361,10 +361,10 @@ class Master(MiniSoC, AMPSoC):
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.comb += platform.request("sfp_tx_disable", 1).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean", 0), clock_pads=platform.request("cdr_clk_clean", 0),
data_pads=[platform.request("sfp", 1)] + data_pads=[platform.request("sfp", 0)] +
# 6 and not 8 to work around Vivado bug (Xilinx CR 1020646) # 6 and not 8 to work around Vivado bug (Xilinx CR 1020646)
[platform.request("rtm_gth", i) for i in range(6)], [platform.request("rtm_gth", i) for i in range(6)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,