From 219dfd898430e0eccab1a34a2eab97c3dede9dc4 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sat, 17 Jun 2017 12:17:48 +0200 Subject: [PATCH] rtio: add one register level for rio and rio_phy resets * This should give Vivado some wiggle room during PnR. * It needs three new clock domains which is ugly. But since AsyncResetSynchronizer can only drive clock domains resets directly there seems to be no other way to add one register level currently. --- artiq/gateware/rtio/core.py | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index b8726bc16..845a0c213 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -308,18 +308,28 @@ class Core(Module, AutoCSR): cmd_reset_phy.attr.add("no_retiming") self.clock_domains.cd_rsys = ClockDomain() + self.clock_domains.cd_rio_rst = ClockDomain() + self.clock_domains.cd_rio_phy_rst = ClockDomain() + self.clock_domains.cd_rio_no_rst = ClockDomain() self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain() self.comb += [ self.cd_rsys.clk.eq(ClockSignal()), - self.cd_rsys.rst.eq(cmd_reset) + self.cd_rsys.rst.eq(cmd_reset), + self.cd_rio_rst.clk.eq(ClockSignal("rtio")), + self.cd_rio_phy_rst.clk.eq(ClockSignal("rtio")), + self.cd_rio_no_rst.clk.eq(ClockSignal("rtio")), + self.cd_rio.clk.eq(ClockSignal("rtio")), + self.cd_rio_phy.clk.eq(ClockSignal("rtio")) + ] + self.specials += [ + AsyncResetSynchronizer(self.cd_rio_rst, cmd_reset), + AsyncResetSynchronizer(self.cd_rio_phy_rst, cmd_reset_phy), + ] + self.sync.rio_no_rst += [ + self.cd_rio.rst.eq(self.cd_rio_rst.rst), + self.cd_rio_phy.rst.eq(self.cd_rio_phy_rst.rst), ] - self.comb += self.cd_rio.clk.eq(ClockSignal("rtio")) - self.specials += AsyncResetSynchronizer( - self.cd_rio, cmd_reset) - self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio")) - self.specials += AsyncResetSynchronizer( - self.cd_rio_phy, cmd_reset_phy) # Managers self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)