From 2180c5af7c0a609137e75334f14b249bae2b7fed Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 13:07:58 +0100 Subject: [PATCH] pipistrello: make pmod[4:8] available as ttls --- artiq/gateware/targets/pipistrello.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 95dae2b29..31e5b4865 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -177,6 +177,15 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) + pmod = self.platform.request("pmod", 0) + + for i in range(4, 8): + phy = ttl_serdes_spartan6.Inout_4X(pmod.d[i], + self.rtio_crg.rtiox4_stb) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, + ofifo_depth=32)) + self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) @@ -194,7 +203,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd ofifo_depth=512, ififo_depth=4)) - pmod = self.platform.request("pmod", 0) spi_pins = Module() spi_pins.cs_n = pmod.d[0] spi_pins.mosi = pmod.d[1] @@ -204,7 +212,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( - phy, ofifo_depth=4, ififo_depth=4)) + phy, ofifo_depth=32, ififo_depth=32)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel())