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@ -27,8 +27,8 @@ from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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def __init__(self, platform):
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self._pll_reset = CSRStorage(reset=1)
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self.pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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@ -60,7 +60,7 @@ class _RTIOCRG(Module, AutoCSR):
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# VCO @ 1GHz when using 125MHz input
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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o_CLKFBOUT=rtio_clk,
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@ -70,7 +70,7 @@ class _RTIOCRG(Module, AutoCSR):
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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MultiReg(pll_locked, self.pll_locked.status)
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]
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]
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