kasli: remove opticlock (moved to kasli_generic)

This commit is contained in:
Sebastien Bourdeauducq 2019-09-09 15:03:10 +08:00
parent 436662be52
commit 21021beb08
2 changed files with 13 additions and 474 deletions

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@ -1,415 +0,0 @@
# This is an example device database that needs to be adapted to your setup.
# The list of devices here is not exhaustive.
core_addr = "hunt.ptb.quartiq.de"
device_db = {
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1e-9}
},
"core_log": {
"type": "controller",
"host": "::1",
"port": 1068,
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dma": {
"type": "local",
"module": "artiq.coredevice.dma",
"class": "CoreDMA"
},
"i2c_switch0": {
"type": "local",
"module": "artiq.coredevice.i2c",
"class": "PCA9548",
"arguments": {"address": 0xe0}
},
"i2c_switch1": {
"type": "local",
"module": "artiq.coredevice.i2c",
"class": "PCA9548",
"arguments": {"address": 0xe2}
},
"ttl0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 0},
},
"ttl1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 1},
},
"ttl2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 2},
},
"ttl3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 3},
},
"ttl4": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 4},
},
"ttl5": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 5},
},
"ttl6": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 6},
},
"ttl7": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 7},
},
"ttl8": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 8},
},
"ttl9": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 9},
},
"ttl10": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 10},
},
"ttl11": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 11},
},
"ttl12": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 12},
},
"ttl13": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 13},
},
"ttl14": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 14},
},
"ttl15": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 15},
},
"ttl16": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 16},
},
"ttl17": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 17},
},
"ttl18": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 18},
},
"ttl19": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 19},
},
"ttl20": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 20},
},
"ttl21": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 21},
},
"ttl22": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 22},
},
"ttl23": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 23},
},
"spi_novogorny0": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 24}
},
"ttl_novogorny0_cnv": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 25}
},
"novogorny0": {
"type": "local",
"module": "artiq.coredevice.novogorny",
"class": "Novogorny",
"arguments": {
"spi_device": "spi_novogorny0",
"cnv_device": "ttl_novogorny0_cnv",
}
},
"spi_urukul0": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 26}
},
"ttl_urukul0_io_update": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 27}
},
"ttl_urukul0_sw0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 28}
},
"ttl_urukul0_sw1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 29}
},
"ttl_urukul0_sw2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 30}
},
"ttl_urukul0_sw3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 31}
},
"urukul0_cpld": {
"type": "local",
"module": "artiq.coredevice.urukul",
"class": "CPLD",
"arguments": {
"spi_device": "spi_urukul0",
"io_update_device": "ttl_urukul0_io_update",
"refclk": 100e6,
"clk_sel": 1
}
},
"urukul0_ch0": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 4,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw0"
}
},
"urukul0_ch1": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 5,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw1"
}
},
"urukul0_ch2": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 6,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw2"
}
},
"urukul0_ch3": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 7,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw3"
}
},
"led0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 32}
},
"led1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 33}
},
"spi_urukul1": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 34}
},
"ttl_urukul1_sync": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLClockGen",
"arguments": {"channel": 35, "acc_width": 4}
},
"ttl_urukul1_io_update": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 36}
},
"urukul1_cpld": {
"type": "local",
"module": "artiq.coredevice.urukul",
"class": "CPLD",
"arguments": {
"spi_device": "spi_urukul1",
"sync_device": "ttl_urukul1_sync",
"io_update_device": "ttl_urukul1_io_update",
"refclk": 100e6,
"clk_sel": 1
}
},
"urukul1_ch0": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 4,
"cpld_device": "urukul1_cpld"
}
},
"urukul1_ch1": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 5,
"cpld_device": "urukul1_cpld"
}
},
"urukul1_ch2": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 6,
"cpld_device": "urukul1_cpld"
}
},
"urukul1_ch3": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 7,
"cpld_device": "urukul1_cpld"
}
},
"spi_zotino0": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 37}
},
"ttl_zotino0_ldac": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 38}
},
"ttl_zotino0_clr": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 39}
},
"zotino0": {
"type": "local",
"module": "artiq.coredevice.zotino",
"class": "Zotino",
"arguments": {
"spi_device": "spi_zotino0",
"ldac_device": "ttl_zotino0_ldac",
"clr_device": "ttl_zotino0_clr"
}
}
}

View File

@ -148,32 +148,30 @@ class StandaloneBase(MiniSoC, AMPSoC):
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")
class Opticlock(StandaloneBase): class Tester(StandaloneBase):
""" """
Opticlock extension variant configuration Configuration for CI tests. Contains the maximum number of different EEMs.
""" """
def __init__(self, hw_rev=None, **kwargs): def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None: if hw_rev is None:
hw_rev = "v1.0" hw_rev = "v1.1"
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_EXT_REF"] = None # self.config["SI5324_EXT_REF"] = None
self.config["EXT_REF_FREQUENCY"] = "100.0"
self.config["RTIO_FREQUENCY"] = "125.0" self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0": if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX # EEM clock fan-out from Si5324, not MMCX
self.comb += self.platform.request("clk_sel").eq(1) self.comb += self.platform.request("clk_sel").eq(1)
self.rtio_channels = [] self.rtio_channels = []
eem.DIO.add_std(self, 0, eem.DIO.add_std(self, 5,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
eem.DIO.add_std(self, 1, edge_counter_cls=edge_counter.SimpleEdgeCounter)
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X,
eem.DIO.add_std(self, 2, ttl_simple.ClockGen)
ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
eem.Novogorny.add_std(self, 3, ttl_serdes_7series.Output_8X) eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
for i in (1, 2): for i in (1, 2):
sfp_ctl = self.platform.request("sfp_ctl", i) sfp_ctl = self.platform.request("sfp_ctl", i)
@ -181,14 +179,9 @@ class Opticlock(StandaloneBase):
self.submodules += phy self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.rtio_channels.append(rtio.Channel.from_phy(phy))
eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X,
ttl_simple.ClockGen)
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels) self.add_rtio(self.rtio_channels)
@ -239,43 +232,6 @@ class SUServo(StandaloneBase):
pads.clkout, self.crg.cd_sys.clk) pads.clkout, self.crg.cd_sys.clk)
class Tester(StandaloneBase):
"""
Configuration for CI tests. Contains the maximum number of different EEMs.
"""
def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.1"
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX
self.comb += self.platform.request("clk_sel").eq(1)
self.rtio_channels = []
eem.DIO.add_std(self, 5,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
edge_counter_cls=edge_counter.SimpleEdgeCounter)
eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X,
ttl_simple.ClockGen)
eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
for i in (1, 2):
sfp_ctl = self.platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels)
class _RTIOClockMultiplier(Module, AutoCSR): class _RTIOClockMultiplier(Module, AutoCSR):
def __init__(self, rtio_clk_freq): def __init__(self, rtio_clk_freq):
self.pll_reset = CSRStorage(reset=1) self.pll_reset = CSRStorage(reset=1)
@ -662,9 +618,7 @@ class Satellite(SatelliteBase):
self.add_rtio(self.rtio_channels) self.add_rtio(self.rtio_channels)
VARIANTS = {cls.__name__.lower(): cls for cls in [ VARIANTS = {cls.__name__.lower(): cls for cls in [Tester, SUServo, Master, Satellite]}
Opticlock, SUServo,
Tester, Master, Satellite]}
def main(): def main():
@ -673,7 +627,7 @@ def main():
builder_args(parser) builder_args(parser)
soc_kasli_args(parser) soc_kasli_args(parser)
parser.set_defaults(output_dir="artiq_kasli") parser.set_defaults(output_dir="artiq_kasli")
parser.add_argument("-V", "--variant", default="opticlock", parser.add_argument("-V", "--variant", default="tester",
help="variant: {} (default: %(default)s)".format( help="variant: {} (default: %(default)s)".format(
"/".join(sorted(VARIANTS.keys())))) "/".join(sorted(VARIANTS.keys()))))
args = parser.parse_args() args = parser.parse_args()