From 207ff918c7394bf55476063d4f5af81a94dff9ff Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 13 Feb 2022 12:50:22 +0800 Subject: [PATCH] coredevice: define ValueError locally work around https://git.m-labs.hk/M-Labs/nac3/issues/189 --- artiq/coredevice/ad53xx.py | 6 ++++++ artiq/coredevice/ad9912.py | 6 ++++++ artiq/coredevice/adf5356.py | 6 ++++++ artiq/coredevice/mirny.py | 6 ++++++ artiq/coredevice/spi2.py | 7 +++++++ artiq/coredevice/urukul.py | 7 +++++++ 6 files changed, 38 insertions(+) diff --git a/artiq/coredevice/ad53xx.py b/artiq/coredevice/ad53xx.py index 0abfd76d9..f09323cc5 100644 --- a/artiq/coredevice/ad53xx.py +++ b/artiq/coredevice/ad53xx.py @@ -17,6 +17,12 @@ from artiq.coredevice.ttl import TTLOut from artiq.coredevice.spi2 import * +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + SPI_AD53XX_CONFIG = (0*SPI_OFFLINE | 1*SPI_END | 0*SPI_INPUT | 0*SPI_CS_POLARITY | 0*SPI_CLK_POLARITY | 1*SPI_CLK_PHASE | diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py index c11b295c2..e563fb823 100644 --- a/artiq/coredevice/ad9912.py +++ b/artiq/coredevice/ad9912.py @@ -10,6 +10,12 @@ from artiq.coredevice.urukul import * from artiq.coredevice.ttl import TTLOut +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + @nac3 class AD9912: """ diff --git a/artiq/coredevice/adf5356.py b/artiq/coredevice/adf5356.py index e783c8088..bb02ee8ba 100644 --- a/artiq/coredevice/adf5356.py +++ b/artiq/coredevice/adf5356.py @@ -20,6 +20,12 @@ from artiq.coredevice.spi2 import * from artiq.coredevice.adf5356_reg import * +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + SPI_CONFIG = ( 0 * SPI_OFFLINE diff --git a/artiq/coredevice/mirny.py b/artiq/coredevice/mirny.py index 9a87dc936..ea18ef881 100644 --- a/artiq/coredevice/mirny.py +++ b/artiq/coredevice/mirny.py @@ -10,6 +10,12 @@ from artiq.coredevice.core import Core from artiq.coredevice.spi2 import * +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + SPI_CONFIG = ( 0 * SPI_OFFLINE | 0 * SPI_END diff --git a/artiq/coredevice/spi2.py b/artiq/coredevice/spi2.py index 3b0147a6a..657cb4cf8 100644 --- a/artiq/coredevice/spi2.py +++ b/artiq/coredevice/spi2.py @@ -14,6 +14,13 @@ from artiq.coredevice.core import Core from artiq.coredevice.rtio import rtio_output, rtio_input_data +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + + __all__ = [ "SPI_DATA_ADDR", "SPI_CONFIG_ADDR", "SPI_OFFLINE", "SPI_END", "SPI_INPUT", diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index f2796a581..ed20b962b 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -8,6 +8,13 @@ from artiq.coredevice.spi2 import * from artiq.coredevice.ttl import TTLOut +# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189 +@nac3 +class ValueError(Exception): + pass + + + SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END | 0 * SPI_INPUT | 1 * SPI_CS_POLARITY | 0 * SPI_CLK_POLARITY | 0 * SPI_CLK_PHASE |