mirror of https://github.com/m-labs/artiq.git
sdram: compact read_level output
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206664afd9
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@ -379,9 +379,9 @@ mod ddr {
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}
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}
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let mean_delay = (min_delay + max_delay) / 2;
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let mean_delay = (min_delay + max_delay) / 2;
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log!(logger, "{}: {} ({} wide), ",
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log!(logger, "{}: {}+-{}, ",
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DQS_SIGNAL_COUNT - n - 1, mean_delay,
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DQS_SIGNAL_COUNT - n - 1, mean_delay,
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max_delay - min_delay);
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max_seen_valid / 2);
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// Set delay to the middle
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// Set delay to the middle
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ddrphy::rdly_dq_rst_write(1);
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ddrphy::rdly_dq_rst_write(1);
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