From 20652ce128af4b1088a0eddd6ecdb2d85808389e Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sun, 9 Apr 2017 13:50:19 +0200 Subject: [PATCH] pdq2: align subsequent writes to end --- artiq/coredevice/pdq2.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/artiq/coredevice/pdq2.py b/artiq/coredevice/pdq2.py index 4fed5076e..5410e7d2f 100644 --- a/artiq/coredevice/pdq2.py +++ b/artiq/coredevice/pdq2.py @@ -98,8 +98,7 @@ class PDQ2: self.bus.set_xfer(self.chip_select, 24, 0) self.bus.write((_PDQ2_CMD(board, 1, mem, 1) << 24) | ((adr & 0x00ff) << 16) | (adr & 0xff00)) - delay_mu(3*self.bus.ref_period_mu - self.bus.xfer_period_mu - - self.bus.write_period_mu) + delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu) self.bus.set_xfer(self.chip_select, 16, 0) for i in range(len(data)//2): self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16))