From 1ff474893df1a07399208c8dddbe3dec09879aa1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Thu, 28 Oct 2021 06:29:56 +0000 Subject: [PATCH] Revert "fastino: make driver filter order configurable" This reverts commit 10c37b87ecfc8b893bb8e5f8b4acc7e3b674ac54. --- artiq/coredevice/fastino.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/artiq/coredevice/fastino.py b/artiq/coredevice/fastino.py index 588a3d436..c60d5d1b1 100644 --- a/artiq/coredevice/fastino.py +++ b/artiq/coredevice/fastino.py @@ -39,15 +39,13 @@ class Fastino: :param core_device: Core device name (default: "core") :param log2_width: Width of DAC channel group (logarithm base 2). Value must match the corresponding value in the RTIO PHY (gateware). - :param order: CIC filter interpolation order. """ - kernel_invariants = {"core", "channel", "width", "order"} + kernel_invariants = {"core", "channel", "width"} - def __init__(self, dmgr, channel, core_device="core", log2_width=0, order=3): + def __init__(self, dmgr, channel, core_device="core", log2_width=0): self.channel = channel << 8 self.core = dmgr.get(core_device) self.width = 1 << log2_width - self.order = order @kernel def init(self): @@ -224,7 +222,8 @@ class Fastino: Returns the actual interpolation rate. The actual overall interpolation gain including gain compensation is - `actual_rate**order/2**ceil(log2(actual_rate**order))`. + `actual_rate**order/2**ceil(log2(actual_rate**order))` + where `order = 3`. """ if rate <= 0 or rate > 1 << 16: raise ValueError("rate out of bounds") @@ -233,14 +232,15 @@ class Fastino: while rate_mantissa > 1 << 6: rate_exponent += 1 rate_mantissa >>= 1 + order = 3 gain = 1 - for i in range(self.order): + for i in range(order): gain *= rate_mantissa gain_exponent = 0 while gain > 1 << gain_exponent: gain_exponent += 1 - gain_exponent += self.order*rate_exponent - assert gain_exponent <= self.order*16 + gain_exponent += order*rate_exponent + assert gain_exponent <= order*16 self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent) return rate_mantissa << rate_exponent @@ -252,6 +252,6 @@ class Fastino: continous DAC updates enabled (see :meth:`set_continuous`). This resets and settles the interpolators. There will be no output - updates for the next `order` input samples. + updates for the next `order = 3` input samples. """ self.write(0x27, channel_mask)