kasli: add SUServo variant (Sampler-Urukul Servo)

This commit is contained in:
Robert Jördens 2018-03-20 18:12:45 +00:00
parent f74d5772f4
commit 1fb5907362
1 changed files with 102 additions and 2 deletions

View File

@ -347,8 +347,8 @@ class Opticlock(_StandaloneBase):
platform.add_extension(_urukul("eem6"))
platform.add_extension(_zotino("eem7"))
# EEM clock fan-out from Si5324, not MMCX
try:
# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
self.comb += platform.request("clk_sel").eq(1)
except ConstraintError:
pass
@ -432,6 +432,104 @@ class Opticlock(_StandaloneBase):
self.add_rtio(rtio_channels)
class SUServo(_StandaloneBase):
"""
SUServo (Sampler-Urukul-Servo) extension variant configuration
"""
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_dio("eem0"))
platform.add_extension(_dio("eem1"))
platform.add_extension(_sampler("eem3", "eem2"))
platform.add_extension(_urukul("eem5", "eem4"))
platform.add_extension(_urukul("eem7", "eem6"))
try:
# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
self.comb += platform.request("clk_sel").eq(1)
except ConstraintError:
pass
rtio_channels = []
for i in range(16):
eem, port = divmod(i, 8)
pads = platform.request("eem{}".format(eem), port)
if i < 4:
cls = ttl_serdes_7series.InOut_8X
else:
cls = ttl_serdes_7series.Output_8X
phy = cls(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM3, EEM2: Sampler
phy = spi2.SPIMaster(self.platform.request("eem3_adc_spi_p"),
self.platform.request("eem3_adc_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
self.platform.request("eem3_pgia_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=2))
for signal in "cnv".split():
pads = platform.request("eem3_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
pads = platform.request("eem3_sdr")
self.specials += DifferentialOutput(1, pads.p, pads.n)
# EEM5 + EEM4: Urukul
phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
self.platform.request("eem5_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem5_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem5_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM7 + EEM6: Urukul
phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
self.platform.request("eem7_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem7_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem7_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
class SYSU(_StandaloneBase):
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
@ -791,13 +889,15 @@ def main():
soc_kasli_args(parser)
parser.set_defaults(output_dir="artiq_kasli")
parser.add_argument("-V", "--variant", default="opticlock",
help="variant: opticlock/sysu/master/satellite "
help="variant: opticlock/suservo/sysu/master/satellite "
"(default: %(default)s)")
args = parser.parse_args()
variant = args.variant.lower()
if variant == "opticlock":
cls = Opticlock
elif variant == "suservo":
cls = SUServo
elif variant == "sysu":
cls = SYSU
elif variant == "master":