mirror of https://github.com/m-labs/artiq.git
kasli: add SUServo variant (Sampler-Urukul Servo)
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@ -347,8 +347,8 @@ class Opticlock(_StandaloneBase):
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platform.add_extension(_urukul("eem6"))
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platform.add_extension(_urukul("eem6"))
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platform.add_extension(_zotino("eem7"))
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platform.add_extension(_zotino("eem7"))
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# EEM clock fan-out from Si5324, not MMCX
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try:
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try:
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# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
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self.comb += platform.request("clk_sel").eq(1)
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self.comb += platform.request("clk_sel").eq(1)
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except ConstraintError:
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except ConstraintError:
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pass
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pass
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@ -432,6 +432,104 @@ class Opticlock(_StandaloneBase):
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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class SUServo(_StandaloneBase):
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"""
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SUServo (Sampler-Urukul-Servo) extension variant configuration
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"""
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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platform = self.platform
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platform.add_extension(_dio("eem0"))
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platform.add_extension(_dio("eem1"))
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platform.add_extension(_sampler("eem3", "eem2"))
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platform.add_extension(_urukul("eem5", "eem4"))
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platform.add_extension(_urukul("eem7", "eem6"))
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try:
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# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
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self.comb += platform.request("clk_sel").eq(1)
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except ConstraintError:
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pass
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rtio_channels = []
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for i in range(16):
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eem, port = divmod(i, 8)
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pads = platform.request("eem{}".format(eem), port)
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if i < 4:
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cls = ttl_serdes_7series.InOut_8X
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else:
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cls = ttl_serdes_7series.Output_8X
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phy = cls(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM3, EEM2: Sampler
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phy = spi2.SPIMaster(self.platform.request("eem3_adc_spi_p"),
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self.platform.request("eem3_adc_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
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phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
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self.platform.request("eem3_pgia_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=2))
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for signal in "cnv".split():
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pads = platform.request("eem3_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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pads = platform.request("eem3_sdr")
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self.specials += DifferentialOutput(1, pads.p, pads.n)
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# EEM5 + EEM4: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
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self.platform.request("eem5_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem5_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem5_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM7 + EEM6: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
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self.platform.request("eem7_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("eem7_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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pads = platform.request("eem7_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in (1, 2):
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sfp_ctl = platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class SYSU(_StandaloneBase):
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class SYSU(_StandaloneBase):
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def __init__(self, **kwargs):
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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_StandaloneBase.__init__(self, **kwargs)
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@ -791,13 +889,15 @@ def main():
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soc_kasli_args(parser)
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("-V", "--variant", default="opticlock",
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: opticlock/sysu/master/satellite "
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help="variant: opticlock/suservo/sysu/master/satellite "
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"(default: %(default)s)")
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"(default: %(default)s)")
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args = parser.parse_args()
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args = parser.parse_args()
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variant = args.variant.lower()
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variant = args.variant.lower()
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if variant == "opticlock":
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if variant == "opticlock":
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cls = Opticlock
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cls = Opticlock
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elif variant == "suservo":
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cls = SUServo
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elif variant == "sysu":
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elif variant == "sysu":
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cls = SYSU
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cls = SYSU
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elif variant == "master":
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elif variant == "master":
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