mirror of https://github.com/m-labs/artiq.git
parent
611bcc4db4
commit
1f15e55021
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@ -360,8 +360,8 @@ class SPIMaster2Handler(WishboneHandler):
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def process_message(self, message):
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self.stb.set_value("1")
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self.stb.set_value("0")
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data = message.data
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if isinstance(message, OutputMessage):
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data = message.data
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address = message.address
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if address == 1:
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logger.debug("SPI config @%d data=0x%08x",
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