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Mark LVDS card and add test for it

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Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
Egor Savkin 2024-08-06 17:08:55 +08:00
parent e38dc59656
commit 1e1aa62c03
2 changed files with 51 additions and 2 deletions
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5
artiq/frontend/artiq_ddb_template.py
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@ -140,6 +140,7 @@ class PeripheralManager:
class_names[peripheral["bank_direction_high"]]
]
channel = count(0)
board = peripheral["board"].lower() if "board" in peripheral else ""
name = [self.get_name("ttl") for _ in range(num_channels)]
for i in range(num_channels):
self.gen("""
@ -147,11 +148,13 @@ class PeripheralManager:
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "{class_name}",
"board": "{board}",
"arguments": {{"channel": 0x{channel:06x}}},
}}""",
name=name[i],
class_name=classes[i // 4],
channel=rtio_offset + next(channel))
channel=rtio_offset + next(channel),
board=board)
if peripheral["edge_counter"]:
for i in range(num_channels):
class_name = classes[i // 4]

48
artiq/frontend/artiq_sinara_tester.py
View File

@ -50,6 +50,8 @@ class SinaraTester(EnvExperiment):
self.leds = dict()
self.ttl_outs = dict()
self.ttl_ins = dict()
self.ttl_lvds_outs = dict()
self.ttl_lvds_ins = dict()
self.urukul_cplds = dict()
self.urukuls = dict()
self.samplers = dict()
@ -76,7 +78,10 @@ class SinaraTester(EnvExperiment):
else:
self.ttl_outs[name] = dev
elif (module, cls) == ("artiq.coredevice.ttl", "TTLInOut"):
self.ttl_ins[name] = self.get_device(name)
if "board" in desc and desc["board"] == "dio_lvds":
self.ttl_lvds[name] = self.get_device(name)
else:
self.ttl_ins[name] = self.get_device(name)
elif (module, cls) == ("artiq.coredevice.urukul", "CPLD"):
self.urukul_cplds[name] = self.get_device(name)
elif (module, cls) == ("artiq.coredevice.ad9910", "AD9910"):
@ -244,6 +249,47 @@ class SinaraTester(EnvExperiment):
else:
print("FAILED")
@kernel
def set_ttl_lvds(self, ttl_to_output, ttl_to_input):
self.core.break_realtime()
ttl_to_input.input()
delay(50*ms)
ttl_to_output.output()
delay(50*ms)
def test_ttl_lvds_outs(self):
print("*** LVDS TTL outputs are tested along with LVDS TTL inputs.")
def test_ttl_lvds(self):
print("*** Testing LVDS TTL.")
print("LVDS TTL channels are tested in groups of 4.")
print("Insert one end of Ethernet cable into first group (marked as CH 0..3)")
print(" of the first LVDS card and press ENTER when done.")
input()
#print(", ".join(self.ttl_lvds))
for i, ttl_chunk in enumerate(chunker(self.ttl_lvds[4:], 4)):
print(f"Connect first group (CH 0..3) to group #{i + 2} (LVDS card #{(i + 1) // 4}, CH{((i + 1) % 4 ) * 4}..{((i + 1) % 4 ) * 4 + 3}). Press ENTER when done.")
input()
for x in range(4):
ttl_in, ttl_in_dev = self.ttl_lvds[0]
ttl_out, ttl_out_dev = ttl_chunk[x]
print(f"Testing {ttl_in} with {ttl_out}... ", end="")
self.set_ttl_lvds(ttl_out_dev, ttl_in_dev)
forward_test_result = self.test_ttl_in(ttl_out_dev, ttl_in_dev)
self.set_ttl_lvds(ttl_in_dev, ttl_out_dev)
reverse_test_result = self.test_ttl_in(ttl_in_dev, ttl_out_dev)
if forward_test_result and reverse_test_result:
print("PASSED")
continue
if not forward_test_result:
print(f"FAILED: from {ttl_out} to {ttl_in}")
if not reverse_test_result:
print(f"FAILED: from {ttl_in} to {ttl_out}")
@kernel
def init_urukul(self, cpld):
self.core.break_realtime()