From 1d2ebbe60f345bdffb941e947fda2b037bff1dab Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 11 Sep 2017 09:06:40 +0800
Subject: [PATCH] rtio/sed: make ON payload layout configurable, add latency
 function

---
 artiq/gateware/rtio/sed/output_network.py     | 23 +++++++++----------
 .../test/rtio/test_sed_output_network.py      | 10 ++++++--
 2 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/artiq/gateware/rtio/sed/output_network.py b/artiq/gateware/rtio/sed/output_network.py
index d993a58aa..edb875b1c 100644
--- a/artiq/gateware/rtio/sed/output_network.py
+++ b/artiq/gateware/rtio/sed/output_network.py
@@ -1,6 +1,9 @@
 from migen import *
 
 
+__all__ = ["latency", "OutputNetwork"]
+
+
 # Based on: https://github.com/Bekbolatov/SortingNetworks/blob/master/src/main/js/gr.js
 def boms_get_partner(n, l, p):
     if p == 1:
@@ -34,21 +37,17 @@ def boms_steps_pairs(lane_count):
     return steps
 
 
-def layout_rtio_payload(fine_ts_width):
-    return [
-        ("channel", 24),
-        ("fine_ts", fine_ts_width),
-        ("address", 16),
-        ("data", 512),
-    ]
+def latency(lane_count):
+    d = log2_int(lane_count)
+    return sum(l for l in range(1, d+1))
 
 
-def layout_node_data(seqn_width, fine_ts_width):
+def layout_node_data(seqn_width, layout_payload):
     return [
         ("valid", 1),
         ("seqn", seqn_width),
         ("replace_occured", 1),
-        ("payload", layout_rtio_payload(fine_ts_width))
+        ("payload", layout_payload)
     ]
 
 
@@ -57,14 +56,14 @@ def cmp_wrap(a, b):
 
 
 class OutputNetwork(Module):
-    def __init__(self, lane_count, seqn_width, fine_ts_width):
-        self.input = [Record(layout_node_data(seqn_width, fine_ts_width))
+    def __init__(self, lane_count, seqn_width, layout_payload):
+        self.input = [Record(layout_node_data(seqn_width, layout_payload))
                       for _ in range(lane_count)]
         self.output = None
 
         step_input = self.input
         for step in boms_steps_pairs(lane_count):
-            step_output = [Record(layout_node_data(seqn_width, fine_ts_width))
+            step_output = [Record(layout_node_data(seqn_width, layout_payload))
                            for _ in range(lane_count)]
 
             for node1, node2 in step:
diff --git a/artiq/gateware/test/rtio/test_sed_output_network.py b/artiq/gateware/test/rtio/test_sed_output_network.py
index 7650678e7..e876637af 100644
--- a/artiq/gateware/test/rtio/test_sed_output_network.py
+++ b/artiq/gateware/test/rtio/test_sed_output_network.py
@@ -9,7 +9,13 @@ LANE_COUNT = 8
 
 
 def simulate(input_events):
-    dut = output_network.OutputNetwork(LANE_COUNT, LANE_COUNT*4, 3)
+    layout_payload = [
+        ("channel", 8),
+        ("fine_ts", 3),
+        ("address", 16),
+        ("data", 512),
+    ]
+    dut = output_network.OutputNetwork(LANE_COUNT, LANE_COUNT*4, layout_payload)
     output = []
     def gen():
         yield
@@ -21,7 +27,7 @@ def simulate(input_events):
         yield
         for n in range(len(input_events)):
             yield dut.input[n].valid.eq(0)
-        for i in range(6):
+        for i in range(output_network.latency(LANE_COUNT)):
             yield
             for x in range(LANE_COUNT):
                 if (yield dut.output[x].valid):