M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

transforms.llvm_ir_generator: use byval for FFI calls where appropriate.

This commit is contained in:
whitequark 2016-01-10 18:31:35 +00:00
parent d1319b83e5
commit 1be9e7576d
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
artiq/compiler/transforms/llvm_ir_generator.py
View File

@ -936,7 +936,18 @@ class LLVMIRGenerator:
return llfun, [llenv] + list(llargs) return llfun, [llenv] + list(llargs)
def _prepare_ffi_call(self, insn): def _prepare_ffi_call(self, insn):
llargs = [self.map(arg) for arg in insn.arguments()] llargs = []
byvals = []
for i, arg in enumerate(insn.arguments()):
llarg = self.map(arg)
if isinstance(llarg.type, (ll.LiteralStructType, ll.IdentifiedStructType)):
llslot = self.llbuilder.alloca(llarg.type)
self.llbuilder.store(llarg, llslot)
llargs.append(llslot)
byvals.append(i)
else:
llargs.append(llarg)
llfunname = insn.target_function().type.name llfunname = insn.target_function().type.name
llfun = self.llmodule.get_global(llfunname) llfun = self.llmodule.get_global(llfunname)
if llfun is None: if llfun is None:
@ -951,6 +962,10 @@ class LLVMIRGenerator:
insn.target_function().type.name) insn.target_function().type.name)
if self.needs_sret(llretty): if self.needs_sret(llretty):
llfun.args[0].add_attribute('sret') llfun.args[0].add_attribute('sret')
byvals = [i + 1 for i in byvals]
for i in byvals:
llfun.args[i].add_attribute('byval')
return llfun, list(llargs) return llfun, list(llargs)
# See session.c:{send,receive}_rpc_value and comm_generic.py:_{send,receive}_rpc_value. # See session.c:{send,receive}_rpc_value and comm_generic.py:_{send,receive}_rpc_value.