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soc/rtio: mini-channels

This commit is contained in:
Sebastien Bourdeauducq 2014-09-11 23:09:43 +08:00
parent 202284d44c
commit 1b58e1510d
3 changed files with 11 additions and 9 deletions
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2
soc/artiqlib/rtio/core.py
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@ -34,7 +34,7 @@ class _RTIOBankO(Module):
for n, chif in enumerate(rbus): for n, chif in enumerate(rbus):
fifo = SyncFIFOBuffered([ fifo = SyncFIFOBuffered([
("timestamp", counter_width+fine_ts_width), ("value", 2)], ("timestamp", counter_width+fine_ts_width), ("value", 2)],
fifo_depth) 2 if chif.mini else fifo_depth)
self.submodules += fifo self.submodules += fifo
fifos.append(fifo) fifos.append(fifo)

10
soc/artiqlib/rtio/phy.py
View File

@ -5,8 +5,8 @@ from artiqlib.rtio.rbus import create_rbus
class SimplePHY(Module): class SimplePHY(Module):
def __init__(self, pads, output_only_pads=set()): def __init__(self, pads, output_only_pads=set(), mini_pads=set()):
self.rbus = create_rbus(0, pads, output_only_pads) self.rbus = create_rbus(0, pads, output_only_pads, mini_pads)
self.loopback_latency = 3 self.loopback_latency = 3
# # # # # #
@ -14,9 +14,7 @@ class SimplePHY(Module):
for pad, chif in zip(pads, self.rbus): for pad, chif in zip(pads, self.rbus):
o_pad = Signal() o_pad = Signal()
self.sync += If(chif.o_stb, o_pad.eq(chif.o_value)) self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
if pad in output_only_pads: if hasattr(chif, "oe"):
self.comb += pad.eq(o_pad)
else:
ts = TSTriple() ts = TSTriple()
i_pad = Signal() i_pad = Signal()
self.sync += ts.oe.eq(chif.oe) self.sync += ts.oe.eq(chif.oe)
@ -28,3 +26,5 @@ class SimplePHY(Module):
self.sync += i_pad_d.eq(i_pad) self.sync += i_pad_d.eq(i_pad)
self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \ self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
chif.i_value.eq(i_pad) chif.i_value.eq(i_pad)
else:
self.comb += pad.eq(o_pad)

8
soc/artiqlib/rtio/rbus.py
View File

@ -2,7 +2,7 @@ from migen.fhdl.std import *
from migen.genlib.record import Record from migen.genlib.record import Record
def create_rbus(fine_ts_bits, pads, output_only_pads): def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
rbus = [] rbus = []
for pad in pads: for pad in pads:
layout = [ layout = [
@ -11,7 +11,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
] ]
if fine_ts_bits: if fine_ts_bits:
layout.append(("o_fine_ts", fine_ts_bits)) layout.append(("o_fine_ts", fine_ts_bits))
if pad not in output_only_pads: if pad not in output_only_pads and pad not in mini_pads:
layout += [ layout += [
("oe", 1), ("oe", 1),
("i_stb", 1), ("i_stb", 1),
@ -20,7 +20,9 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
] ]
if fine_ts_bits: if fine_ts_bits:
layout.append(("i_fine_ts", fine_ts_bits)) layout.append(("i_fine_ts", fine_ts_bits))
rbus.append(Record(layout)) chif = Record(layout)
chif.mini = pad in mini_pads
rbus.append(chif)
return rbus return rbus