diff --git a/soc/artiqlib/rtio/core.py b/soc/artiqlib/rtio/core.py
index a4f298b85..5c7351200 100644
--- a/soc/artiqlib/rtio/core.py
+++ b/soc/artiqlib/rtio/core.py
@@ -34,7 +34,7 @@ class _RTIOBankO(Module):
         for n, chif in enumerate(rbus):
             fifo = SyncFIFOBuffered([
                 ("timestamp", counter_width+fine_ts_width), ("value", 2)],
-                fifo_depth)
+                2 if chif.mini else fifo_depth)
             self.submodules += fifo
             fifos.append(fifo)
 
diff --git a/soc/artiqlib/rtio/phy.py b/soc/artiqlib/rtio/phy.py
index 31b7e5870..f1c34ccfa 100644
--- a/soc/artiqlib/rtio/phy.py
+++ b/soc/artiqlib/rtio/phy.py
@@ -5,8 +5,8 @@ from artiqlib.rtio.rbus import create_rbus
 
 
 class SimplePHY(Module):
-    def __init__(self, pads, output_only_pads=set()):
-        self.rbus = create_rbus(0, pads, output_only_pads)
+    def __init__(self, pads, output_only_pads=set(), mini_pads=set()):
+        self.rbus = create_rbus(0, pads, output_only_pads, mini_pads)
         self.loopback_latency = 3
 
         # # #
@@ -14,9 +14,7 @@ class SimplePHY(Module):
         for pad, chif in zip(pads, self.rbus):
             o_pad = Signal()
             self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
-            if pad in output_only_pads:
-                self.comb += pad.eq(o_pad)
-            else:
+            if hasattr(chif, "oe"):
                 ts = TSTriple()
                 i_pad = Signal()
                 self.sync += ts.oe.eq(chif.oe)
@@ -28,3 +26,5 @@ class SimplePHY(Module):
                 self.sync += i_pad_d.eq(i_pad)
                 self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
                     chif.i_value.eq(i_pad)
+            else:
+                self.comb += pad.eq(o_pad)
diff --git a/soc/artiqlib/rtio/rbus.py b/soc/artiqlib/rtio/rbus.py
index 821b3c2a6..9eb46f44c 100644
--- a/soc/artiqlib/rtio/rbus.py
+++ b/soc/artiqlib/rtio/rbus.py
@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import Record
 
 
-def create_rbus(fine_ts_bits, pads, output_only_pads):
+def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
     rbus = []
     for pad in pads:
         layout = [
@@ -11,7 +11,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
         ]
         if fine_ts_bits:
             layout.append(("o_fine_ts", fine_ts_bits))
-        if pad not in output_only_pads:
+        if pad not in output_only_pads and pad not in mini_pads:
             layout += [
                 ("oe", 1),
                 ("i_stb", 1),
@@ -20,7 +20,9 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
             ]
             if fine_ts_bits:
                 layout.append(("i_fine_ts", fine_ts_bits))
-        rbus.append(Record(layout))
+        chif = Record(layout)
+        chif.mini = pad in mini_pads
+        rbus.append(chif)
     return rbus