gateware/rt2wb: only input when active

2024-12-25 19:28:26 +08:00 · 2016-02-29 14:56:29 +01:00 · 2016-02-29 14:56:29 +01:00 · 1b08e65fa1
commit 1b08e65fa1
parent 6903a1d88a
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/phy/wishbone.py
+++ b/artiq/gateware/rtio/phy/wishbone.py
@ -39,6 +39,6 @@ class RT2WB(Module):
            wb.cyc.eq(active),
            wb.stb.eq(active),

-            self.rtlink.i.stb.eq(wb.ack & ~wb.we),
+            self.rtlink.i.stb.eq(active & wb.ack & ~wb.we),
            self.rtlink.i.data.eq(wb.dat_r)
        ]