From 1a1edb13bf7fa25fa41f659a384c4708d3faa294 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Tue, 2 May 2017 18:05:41 +0200
Subject: [PATCH] pdq2 -> pdq

---
 artiq/coredevice/{pdq2.py => pdq.py}  | 34 +++++++++++++--------------
 doc/manual/core_drivers_reference.rst |  4 ++--
 2 files changed, 19 insertions(+), 19 deletions(-)
 rename artiq/coredevice/{pdq2.py => pdq.py} (83%)

diff --git a/artiq/coredevice/pdq2.py b/artiq/coredevice/pdq.py
similarity index 83%
rename from artiq/coredevice/pdq2.py
rename to artiq/coredevice/pdq.py
index a4d35d04a..e7acd36aa 100644
--- a/artiq/coredevice/pdq2.py
+++ b/artiq/coredevice/pdq.py
@@ -2,7 +2,7 @@ from artiq.language.core import kernel, portable, delay_mu
 from artiq.coredevice import spi
 
 
-_PDQ2_SPI_CONFIG = (
+_PDQ_SPI_CONFIG = (
         0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
         0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
         0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX
@@ -10,16 +10,16 @@ _PDQ2_SPI_CONFIG = (
 
 
 @portable
-def _PDQ2_CMD(board, is_mem, adr, we):
+def _PDQ_CMD(board, is_mem, adr, we):
     return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
 
 
-_PDQ2_ADR_CONFIG = 0
-_PDQ2_ADR_CRC = 1
-_PDQ2_ADR_FRAME = 2
+_PDQ_ADR_CONFIG = 0
+_PDQ_ADR_CRC = 1
+_PDQ_ADR_FRAME = 2
 
 
-class PDQ2:
+class PDQ:
     """
 
     :param spi_device: Name of the SPI bus this device is on.
@@ -49,18 +49,18 @@ class PDQ2:
         # write: 4*8ns >= 20ns = 2*clk (clock de-glitching 50MHz)
         # read: 15*8*ns >= ~100ns = 5*clk (clk de-glitching latency + miso
         #   latency)
-        self.bus.set_config_mu(_PDQ2_SPI_CONFIG, write_div, read_div)
+        self.bus.set_config_mu(_PDQ_SPI_CONFIG, write_div, read_div)
         self.bus.set_xfer(self.chip_select, 16, 0)
 
     @kernel
     def write_reg(self, adr, data, board):
-        self.bus.write((_PDQ2_CMD(board, 0, adr, 1) << 24) | (data << 16))
+        self.bus.write((_PDQ_CMD(board, 0, adr, 1) << 24) | (data << 16))
         delay_mu(self.bus.ref_period_mu)  # get to 20ns min cs high
 
     @kernel
     def read_reg(self, adr, board):
         self.bus.set_xfer(self.chip_select, 16, 8)
-        self.bus.write(_PDQ2_CMD(board, 0, adr, 0) << 24)
+        self.bus.write(_PDQ_CMD(board, 0, adr, 0) << 24)
         delay_mu(self.bus.ref_period_mu)  # get to 20ns min cs high
         self.bus.read_async()
         self.bus.set_xfer(self.chip_select, 16, 0)
@@ -71,32 +71,32 @@ class PDQ2:
                      trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
         config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
                   (trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
-        self.write_reg(_PDQ2_ADR_CONFIG, config, board)
+        self.write_reg(_PDQ_ADR_CONFIG, config, board)
 
     @kernel
     def read_config(self, board=0xf):
-        return self.read_reg(_PDQ2_ADR_CONFIG, board)
+        return self.read_reg(_PDQ_ADR_CONFIG, board)
 
     @kernel
     def write_crc(self, crc, board=0xf):
-        self.write_reg(_PDQ2_ADR_CRC, crc, board)
+        self.write_reg(_PDQ_ADR_CRC, crc, board)
 
     @kernel
     def read_crc(self, board=0xf):
-        return self.read_reg(_PDQ2_ADR_CRC, board)
+        return self.read_reg(_PDQ_ADR_CRC, board)
 
     @kernel
     def write_frame(self, frame, board=0xf):
-        self.write_reg(_PDQ2_ADR_FRAME, frame, board)
+        self.write_reg(_PDQ_ADR_FRAME, frame, board)
 
     @kernel
     def read_frame(self, board=0xf):
-        return self.read_reg(_PDQ2_ADR_FRAME, board)
+        return self.read_reg(_PDQ_ADR_FRAME, board)
 
     @kernel
     def write_mem(self, mem, adr, data, board=0xf):  # FIXME: m-labs/artiq#714
         self.bus.set_xfer(self.chip_select, 24, 0)
-        self.bus.write((_PDQ2_CMD(board, 1, mem, 1) << 24) |
+        self.bus.write((_PDQ_CMD(board, 1, mem, 1) << 24) |
                        ((adr & 0x00ff) << 16) | (adr & 0xff00))
         delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
         self.bus.set_xfer(self.chip_select, 16, 0)
@@ -112,7 +112,7 @@ class PDQ2:
         if not n:
             return
         self.bus.set_xfer(self.chip_select, 24, 8)
-        self.bus.write((_PDQ2_CMD(board, 1, mem, 0) << 24) |
+        self.bus.write((_PDQ_CMD(board, 1, mem, 0) << 24) |
                        ((adr & 0x00ff) << 16) | (adr & 0xff00))
         delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
         self.bus.set_xfer(self.chip_select, 0, 16)
diff --git a/doc/manual/core_drivers_reference.rst b/doc/manual/core_drivers_reference.rst
index 09d9e8088..bbd0e39c6 100644
--- a/doc/manual/core_drivers_reference.rst
+++ b/doc/manual/core_drivers_reference.rst
@@ -69,8 +69,8 @@ These drivers are for the core device and the peripherals closely integrated int
 .. automodule:: artiq.coredevice.sawg
     :members:
 
-:mod:`artiq.coredevice.pdq2` module
+:mod:`artiq.coredevice.pdq` module
 -----------------------------------
 
-.. automodule:: artiq.coredevice.pdq2
+.. automodule:: artiq.coredevice.pdq
     :members: