mirror of https://github.com/m-labs/artiq.git
firmware/ad9154: cleanup DAC init
- Split dac_setup in dac_reset, dat_detect & dac_setup. - Only do one reset/detection. - Configure before doing SYSREF scan (otherwise scan don't work at the first scan after power up). - Do the spi_setup in each function.
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@ -131,7 +131,8 @@ const JESD_SETTINGS: JESDSettings = JESDSettings {
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jesdv: 1
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};
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fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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fn dac_reset(dacno: u8) {
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spi_setup(dacno);
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// reset
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write(ad9154_reg::SPI_INTFCONFA,
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1*ad9154_reg::SOFTRESET_M | 1*ad9154_reg::SOFTRESET |
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@ -145,12 +146,20 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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0*ad9154_reg::ADDRINC_M | 0*ad9154_reg::ADDRINC |
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1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
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clock::spin_us(100);
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}
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fn dac_detect(dacno: u8) -> Result<(), &'static str> {
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spi_setup(dacno);
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if (read(ad9154_reg::PRODIDH) as u16) << 8 | (read(ad9154_reg::PRODIDL) as u16) != 0x9154 {
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return Err("invalid AD9154 identification");
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} else {
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info!("AD9154-{} found", dacno);
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}
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Ok(())
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}
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fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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spi_setup(dacno);
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info!("AD9154-{} initializing...", dacno);
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write(ad9154_reg::PWRCNTRL0,
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0*ad9154_reg::PD_DAC0 | 0*ad9154_reg::PD_DAC1 |
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@ -400,7 +409,8 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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}
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#[allow(dead_code)]
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fn dac_status() {
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fn dac_status(dacno: u8) {
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spi_setup(dacno);
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info!("SERDES_PLL_LOCK: {}",
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(read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB));
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info!("");
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@ -452,7 +462,8 @@ fn dac_status() {
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info!("NITDISPARITY: 0x{:02x}", read(ad9154_reg::NIT_W));
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}
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fn dac_monitor() {
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fn dac_monitor(dacno: u8) {
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spi_setup(dacno);
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write(ad9154_reg::IRQ_STATUS0, 0x00);
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write(ad9154_reg::IRQ_STATUS1, 0x00);
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write(ad9154_reg::IRQ_STATUS2, 0x00);
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@ -497,6 +508,7 @@ fn dac_monitor() {
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fn dac_prbs(dacno: u8) -> Result<(), &'static str> {
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let mut prbs_errors: u32 = 0;
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spi_setup(dacno);
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/* follow phy prbs testing (p58 of ad9154 datasheet) */
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info!("AD9154-{} running PRBS test...", dacno);
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@ -572,7 +584,7 @@ fn dac_cfg(dacno: u8) -> Result<(), &'static str> {
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jesd_enable(dacno, false);
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clock::spin_us(10000);
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jesd_enable(dacno, true);
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dac_monitor();
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dac_monitor(dacno);
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clock::spin_us(50000);
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let t = clock::get_ms();
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while !jesd_ready(dacno) {
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@ -654,10 +666,15 @@ pub fn init() -> Result<(), &'static str> {
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for dacno in 0..csr::AD9154.len() {
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let dacno = dacno as u8;
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dac_sysref_scan(dacno);
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dac_sysref_cfg(dacno, 88);
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// Reset the DAC, detect and configure it
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dac_reset(dacno);
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dac_detect(dacno)?;
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dac_cfg_retry(dacno)?;
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// Run the PRBS and SYSREF scan tests
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dac_prbs(dacno)?;
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dac_sysref_scan(dacno);
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// Set SYSREF phase and reconfigure the DAC
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dac_sysref_cfg(dacno, 88);
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dac_cfg_retry(dacno)?;
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}
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