mirror of https://github.com/m-labs/artiq.git
wrpll/thls: implement signed numbers
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efc43142a6
commit
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@ -132,13 +132,28 @@ class ASTCompiler:
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output = self.get_ssa_reg()
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self.program.append(cons(inputs=inputs, outputs=[output]))
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return output
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elif isinstance(node, ast.Num):
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if node.n in self.constants:
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return self.constants[node.n]
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elif isinstance(node, (ast.Num, ast.UnaryOp)):
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if isinstance(node, ast.UnaryOp):
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if not isinstance(node.operand, ast.Num):
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raise NotImplementedError
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if isinstance(node.op, ast.UAdd):
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transform = lambda x: x
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elif isinstance(node.op, ast.USub):
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transform = operator.neg
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elif isinstance(node.op, ast.Invert):
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transform = operator.invert
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else:
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raise NotImplementedError
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node = node.operand
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else:
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transform = lambda x: x
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n = transform(node.n)
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if n in self.constants:
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return self.constants[n]
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else:
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r = len(self.data)
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self.data.append(node.n)
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self.constants[node.n] = r
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self.data.append(n)
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self.constants[n] = r
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return r
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elif isinstance(node, ast.Name):
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return self.names[node.id]
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@ -357,10 +372,10 @@ def compile(processor, function):
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class BaseUnit(Module):
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def __init__(self, data_width):
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self.stb_i = Signal()
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self.i0 = Signal(data_width)
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self.i1 = Signal(data_width)
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self.i0 = Signal((data_width, True))
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self.i1 = Signal((data_width, True))
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self.stb_o = Signal()
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self.o = Signal(data_width)
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self.o = Signal((data_width, True))
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class NopUnit(BaseUnit):
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@ -436,10 +451,10 @@ class OutputUnit(BaseUnit):
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class ProcessorImpl(Module):
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def __init__(self, pd, program, data):
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self.input_stb = Signal()
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self.input = Signal(pd.data_width)
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self.input = Signal((pd.data_width, True))
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self.output_stb = Signal()
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self.output = Signal(pd.data_width)
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self.output = Signal((pd.data_width, True))
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self.busy = Signal()
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@ -569,7 +584,7 @@ def foo(x):
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def simple_test(x):
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return min((x*2 >> 1) + 2, 10)
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return min((x*-2 >> 1) + 2 - 1000, 10)
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if __name__ == "__main__":
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