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libboard: fix JESD reset release

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This commit is contained in:
Sebastien Bourdeauducq 2017-11-29 18:18:41 +08:00
parent bb3d6ef84a
commit 19498e59f9
1 changed files with 3 additions and 3 deletions
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6
artiq/firmware/libboard/ad9154.rs
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@ -35,9 +35,9 @@ fn read(addr: u16) -> u8 {
}
}
fn jesd_reset(dacno: u8, rst: bool) {
fn jesd_unreset() {
unsafe {
(csr::AD9154[dacno as usize].jesd_jreset_write)(if rst {1} else {0})
csr::ad9154_crg::jreset_write(0)
}
}
@ -425,7 +425,7 @@ fn cfg(dacno: u8) -> Result<(), &'static str> {
spi_setup(dacno);
// Release the JESD clock domain reset late, as we need to
// set up clock chips before.
jesd_reset(dacno, false);
jesd_unreset();
jesd_enable(dacno, false);
jesd_prbs(dacno, false);