From 18e3f58c22e5c1b5a8e1c9577b4f587637052e70 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 8 Dec 2016 16:14:32 +0100 Subject: [PATCH] sawg: reduce coefficient width --- artiq/gateware/dsp/sawg.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py index 4001eb09d..fb4d45eac 100644 --- a/artiq/gateware/dsp/sawg.py +++ b/artiq/gateware/dsp/sawg.py @@ -146,9 +146,9 @@ class Channel(Module, SatAddMixin): self.submodules.a1 = a1 = SplineParallelDDS(widths, orders) self.submodules.a2 = a2 = SplineParallelDDS(widths, orders) - coeff = [[int(round((1 << 26) * ci)) for ci in c] + coeff = [[int(round((1 << 18)*ci)) for ci in c] for c in halfgen4_cascade(parallelism, width=.4, order=8)] - hbf = [ParallelHBFUpsampler(coeff, width=width, shift=25) + hbf = [ParallelHBFUpsampler(coeff, width=width, shift=17) for i in range(2)] self.submodules.b = b = SplineParallelDUC( widths._replace(a=len(a1.xo[0]), f=widths.f - width), orders,