diff --git a/artiq/gateware/drtio/wrpll/ddmtd.py b/artiq/gateware/drtio/wrpll/ddmtd.py
index 48ca5966f..512638d8c 100644
--- a/artiq/gateware/drtio/wrpll/ddmtd.py
+++ b/artiq/gateware/drtio/wrpll/ddmtd.py
@@ -130,7 +130,7 @@ class DDMTD(Module, AutoCSR):
 
 
 class Collector(Module):
-    """ Generates loop filter inputs from DDMTD outputs.
+    """Generates loop filter inputs from DDMTD outputs.
 
     When the WR PLL is locked, the following ideally (no noise etc) obtain:
     - f_main = f_ref
@@ -234,7 +234,6 @@ class Collector(Module):
 
 
 def test_collector_main():
-
     N = 2
     collector = Collector(N=N)
     # check collector phase unwrapping
@@ -277,7 +276,6 @@ def test_collector_main():
 
 
 def test_collector_helper():
-
     N = 3
     collector = Collector(N=N)
     # check collector phase unwrapping
@@ -304,6 +302,7 @@ def test_collector_helper():
 
     run_simulation(collector, generator())
 
+
 if __name__ == "__main__":
     test_collector_main()
     test_collector_helper()