From 17b5388259397280547415c5386bfef488b7bbae Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 5 Apr 2017 16:38:56 +0000 Subject: [PATCH] gateware: remove one stray CRI arbiter remnant. --- artiq/gateware/drtio/rt_controller_master.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py index bd533cef6..2761c9e83 100644 --- a/artiq/gateware/drtio/rt_controller_master.py +++ b/artiq/gateware/drtio/rt_controller_master.py @@ -37,7 +37,6 @@ class RTController(Module): def __init__(self, rt_packet, channel_count, fine_ts_width): self.csrs = _CSRs() self.cri = cri.Interface() - self.comb += self.cri.arb_gnt.eq(1) # protocol errors err_unknown_packet_type = Signal() @@ -45,7 +44,7 @@ class RTController(Module): signal_fifo_space_timeout = Signal() err_fifo_space_timeout = Signal() self.sync.sys_with_rst += [ - If(self.csrs.protocol_error.re, + If(self.csrs.protocol_error.re, If(self.csrs.protocol_error.r[0], err_unknown_packet_type.eq(0)), If(self.csrs.protocol_error.r[1], err_packet_truncated.eq(0)), If(self.csrs.protocol_error.r[2], err_fifo_space_timeout.eq(0)) @@ -70,7 +69,7 @@ class RTController(Module): tsc_correction = Signal(64) self.csrs.tsc_correction.storage.attr.add("no_retiming") self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction) - self.comb += [ + self.comb += [ rt_packet.tsc_value.eq( self.counter.value_rtio + tsc_correction), self.csrs.set_time.w.eq(rt_packet.set_time_stb)