From 16b7f8f50c8a65b8a70e383589710a97c44e0563 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 7 Apr 2017 23:57:08 +0200 Subject: [PATCH] sma_spi: cri/cd changes --- artiq/gateware/targets/kc705_sma_spi.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kc705_sma_spi.py b/artiq/gateware/targets/kc705_sma_spi.py index cbdf74a52..2ca47ccce 100644 --- a/artiq/gateware/targets/kc705_sma_spi.py +++ b/artiq/gateware/targets/kc705_sma_spi.py @@ -67,8 +67,6 @@ class _RTIOCRG(Module, AutoCSR): ] - - _sma_spi = [ ("sma_spi", 0, Subsignal("clk", Pins("Y23")), # user_sma_gpio_p @@ -122,12 +120,14 @@ class SMA_SPI(_NIST_Ions): self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() - self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri]) + self.register_kernel_cpu_csrdevice("cri_con") self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj")