From 165ef20ffa88829e7b9b9a4410eb33818ebce6e1 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sun, 28 Jun 2015 21:24:57 -0600 Subject: [PATCH] pipistrello: drop rtio fifos for invisible leds the main board leds are all under the adapter board also tweak fifo depths a bit in a feeble attempt to circumvent a ISE hang (par phase 4) --- soc/targets/artiq_pipistrello.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index ddc42a8dd..be7ba6312 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -105,12 +105,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) + rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) - for i in range(2, 5): - phy = ttl_simple.Output(platform.request("user_led", i)) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) self.add_constant("RTIO_TTL_COUNT", len(rtio_channels)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))